公开(公告)号：US07417284B2

公开(公告)日：2008-08-26

申请号：US11301249

申请日：2005-12-13

申请人： Shoichi Yamauchi ,  Yoshiyuki Hattori ,  Kyoko Okada

发明人： Shoichi Yamauchi ,  Yoshiyuki Hattori ,  Kyoko Okada

IPC分类号： H01L29/76 ,  H01L31/062

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/66734 ,  H01L29/7813

摘要： A semiconductor device having SJ structure has a peripheral region having a higher withstand voltage than the withstand voltage of the cell region. A semiconductor upper layer including second conductivity-type impurities and a semiconductor lower layer including first conductivity-type impurities whose concentration is lower than the first portion region constituting the combination of the cell region are formed in the semiconductor layer of the peripheral region. A field oxide layer is formed on a surface of the semiconductor upper layer.

摘要翻译： 具有SJ结构的半导体器件具有比电池区域的耐电压更高的耐受电压的周边区域。 在周边区域的半导体层中形成有包含第二导电型杂质的半导体上层和包含第一导电型杂质的半导体下层，该第一导电型杂质的浓度低于构成该单元区域组合的第一部分区域。 在半导体上层的表面上形成场氧化物层。

公开(公告)号：US20080054325A1

公开(公告)日：2008-03-06

申请号：US11892819

申请日：2007-08-28

申请人： Shigeki Takahashi ,  Takashi Nakano ,  Nozomu Akagi ,  Yasushi Higuchi ,  Tetsuo Fujii ,  Yoshiyuki Hattori ,  Makoto Kuwahara ,  Kyoko Okada

发明人： Shigeki Takahashi ,  Takashi Nakano ,  Nozomu Akagi ,  Yasushi Higuchi ,  Tetsuo Fujii ,  Yoshiyuki Hattori ,  Makoto Kuwahara ,  Kyoko Okada

IPC分类号： H01L27/06

CPC分类号： H01L27/0727 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7817 ,  H01L29/7821

摘要： A semiconductor device includes: a semiconductor substrate; a lateral MOS transistor disposed in the substrate; a Zener diode disposed in the substrate; and a capacitor disposed in the substrate. The transistor includes a drain and a gate, and the diode and the capacitor are coupled in series between the drain and the gate. This device has minimized dimensions and high switching speed. Further, both of a switching loss and a surge voltage are improved.

摘要翻译： 半导体器件包括：半导体衬底; 设置在基板中的横向MOS晶体管; 设置在基板中的齐纳二极管; 以及设置在基板中的电容器。 晶体管包括漏极和栅极，并且二极管和电容器串联耦合在漏极和栅极之间。 该设备具有最小的尺寸和高切换速度。 此外，改善了开关损耗和浪涌电压两者。

公开(公告)号：US20070145479A1

公开(公告)日：2007-06-28

申请号：US11645792

申请日：2006-12-27

申请人： Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Yoshiyuki Hattori ,  Kyoko Okada

发明人： Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Yoshiyuki Hattori ,  Kyoko Okada

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/36

摘要： A semiconductor device includes: two main electrodes; multiple first regions; and multiple second regions. The first region having a first impurity concentration and a first width and the second region having a second impurity concentration and a second width are alternately repeated. A product of the first impurity concentration and the first width is equal to a product of the second impurity concentration and the second width. The first width is equal to or smaller than 4.5 μm. The first impurity concentration is lower than a predetermined concentration satisfying a RESURF condition. A ratio between on-state resistances of the device at 27° C. and at 150° C. is smaller than 1.8.

摘要翻译： 半导体器件包括：两个主电极; 多个第一区域; 和多个第二区域。 交替重复具有第一杂质浓度和第一宽度的第一区域和具有第二杂质浓度和第二宽度的第二区域。 第一杂质浓度和第一宽度的乘积等于第二杂质浓度与第二宽度的乘积。 第一宽度等于或小于4.5μm。 第一杂质浓度低于满足RESURF条件的预定浓度。 器件在27°C和150°C的导通电阻之间的比值小于1.8。

公开(公告)号：US20060124997A1

公开(公告)日：2006-06-15

申请号：US11301249

申请日：2005-12-13

申请人： Shoichi Yamauchi ,  Yoshiyuki Hattori ,  Kyoko Okada

发明人： Shoichi Yamauchi ,  Yoshiyuki Hattori ,  Kyoko Okada

IPC分类号： H01L29/94 ,  H01L29/76

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/66734 ,  H01L29/7813

摘要： A semiconductor device having SJ structure has a peripheral region having a higher withstand voltage than the withstand voltage of the cell region. A semiconductor upper layer including second conductivity-type impurities and a semiconductor lower layer including first conductivity-type impurities whose concentration is lower than the first portion region constituting the combination of the cell region are formed in the semiconductor layer of the peripheral region. A field oxide layer is formed on a surface of the semiconductor upper layer.

摘要翻译： 具有SJ结构的半导体器件具有比电池区域的耐电压更高的耐受电压的周边区域。 在周边区域的半导体层中形成有包含第二导电型杂质的半导体上层和包含第一导电型杂质的半导体下层，该第一导电型杂质的浓度低于构成该单元区域组合的第一部分区域。 在半导体上层的表面上形成场氧化物层。