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164 条记录 (耗时 0.04 秒)

    Clock supplying circuit and integrated circuit device using it
    31.
    发明授权
    Clock supplying circuit and integrated circuit device using it 失效
    时钟供电电路和使用它的集成电路器件

    公开(公告)号：US6150866A

    公开(公告)日：2000-11-21

    申请号：US977690

    申请日：1997-11-24

    申请人： Satoshi Eto ,  Toshikazu Nakamura

    发明人： Satoshi Eto ,  Toshikazu Nakamura

    IPC分类号： G06F1/10 ,  H03K5/13 ,  H03K3/00

    CPC分类号： H03K5/131 ,  G06F1/10 ,  H03K5/133

    摘要： A clock supplying circuit that supplies a clock to a plurality of controlled circuits 451-454 arranged in respectively different positions. A forward and backward wiring 41, 42 and an internal clock supply wiring 43 are arranged along controlled circuits. A main clock drive circuit 40 is for outputting a first clock to the forward wiring 41 and is for outputting a second shorter phase than the first clock to the internal clock supply wiring 43. A plurality of local clock drive circuits 441-444 arranged close to the controlled circuits, are supplied with a forward clock propagated along the forward wiring and with a back clock propagated along the backward wiring, and are also supplied with the second clock, for delaying the phase of the supplied second clock so as to coincide with a phase intermediate the forward clock and the back clock, and for supplying the delayed clock of the second clock to the respectively corresponding controlled circuits as local clock.

    摘要翻译： 时钟提供电路，其将时钟提供给分别布置在不同位置的多个受控电路451-454。 正向和反向布线41,42和内部​​时钟供应布线43沿着受控电路布置。 主时钟驱动电路40用于向正向配线41输出第一时钟，并将第一时钟与第一时钟相比输出到内部时钟供给配线43.多个本地时钟驱动电路441-444， 受控电路被提供有沿着正向布线传播的正向时钟和沿着后向布线传播的后向时钟，并且还被提供有第二时钟，用于延迟所提供的第二时钟的相位以与一个 相位在正向时钟和后向时钟之间，并且用于将第二时钟的延迟时钟提供给分别对应的受控电路作为本地时钟。

    Semiconductor integrated circuit
    32.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US07193922B2

    公开(公告)日：2007-03-20

    申请号：US10968072

    申请日：2004-10-20

    申请人： Toshiya Miyo ,  Toshikazu Nakamura ,  Satoshi Eto

    发明人： Toshiya Miyo ,  Toshikazu Nakamura ,  Satoshi Eto

    IPC分类号： G11C8/00 ,  G11C5/06

    CPC分类号： G11C11/4097

    摘要： Second memory cells of a second memory block each have an area 2a times (a is a positive integer) that of each first memory cell of a first memory block. Sizing the first and second memory cells in a predetermined ratio can make easily identical the dimensions of the first memory block and the second memory block. Consequently, it is possible to easily align peripheral circuits to lie around the plurality of first and second memory blocks, such as decoders. This also facilitates the wiring of signal lines to be connected to the peripheral circuits. This makes it possible to improve the layout design efficiency for a semiconductor integrated circuit. Thus, a plurality of types of memory blocks can be formed on a semiconductor integrated circuit efficiently. The semiconductor integrated circuit can be prevented from increasing in chip size depending on the layout design, owing to its simplified layout.

    摘要翻译： 第二存储器块的第二存储单元分别具有第一存储器块的每个第一存储器单元的区域2（a）为正整数）。 以预定比例对第一和第二存储器单元进行尺寸可以使得第一存储块和第二存储块的尺寸容易相同。 因此，可以容易地将外围电路对准在诸如解码器之类的多个第一和第二存储器块周围。 这也有助于连接到外围电路的信号线的布线。 这使得可以提高半导体集成电路的布局设计效率。 因此，可以有效地在半导体集成电路上形成多种类型的存储块。 由于布局简单，可以防止半导体集成电路因布局设计而增加芯片尺寸。

    Semiconductor device
    35.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US06961881B2

    公开(公告)日：2005-11-01

    申请号：US10122181

    申请日：2002-04-16

    申请人： Masafumi Yamazaki ,  Takaaki Suzuki ,  Toshikazu Nakamura ,  Satoshi Eto ,  Toshiya Miyo ,  Ayako Sato ,  Takayuki Yoneda ,  Noriko Kawamura

    发明人： Masafumi Yamazaki ,  Takaaki Suzuki ,  Toshikazu Nakamura ,  Satoshi Eto ,  Toshiya Miyo ,  Ayako Sato ,  Takayuki Yoneda ,  Noriko Kawamura

    IPC分类号： G11C29/00 ,  G11C29/36 ,  G11C29/48

    CPC分类号： G11C29/48 ,  G11C29/36

    摘要： A logic chip and a memory chip to be accessed by the logic chip are mounted in a single package. A pattern generator of the logic chip operates during a first test mode to generate internal test pattern for the memory chip. A pattern selector selects, during the first test mode, the internal test pattern outputted from the pattern generator, selects, during a second test mode, an external test pattern supplied via a test terminal, and outputs the selected test pattern to the memory chip. The memory chip mounted in the package is tested by use of, in accordance with a mode selecting signal, either the internal test pattern in the first test mode, generated within the logic chip, or the external test pattern in the second test mode, supplied from the exterior.

    摘要翻译： 由逻辑芯片访问的逻辑芯片和存储器芯片安装在单个封装中。 逻辑芯片的模式发生器在第一测试模式下操作以产生用于存储器芯片的内部测试模式。 模式选择器在第一测试模式期间选择从模式发生器输出的内部测试模式，在第二测试模式期间，选择通过测试终端提供的外部测试模式，并将所选择的测试模式输出到存储芯片。 通过使用模式选择信号，在第二测试模式中使用在逻辑芯片内产生的第一测试模式中的内部测试模式或外部测试模式来测试安装在封装中的存储芯片， 从外部。

    Semiconductor memory
    37.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US07064998B2

    公开(公告)日：2006-06-20

    申请号：US11215045

    申请日：2005-08-31

    申请人： Toshikazu Nakamura ,  Satoshi Eto ,  Toshiya Miyo

    发明人： Toshikazu Nakamura ,  Satoshi Eto ,  Toshiya Miyo

    IPC分类号： G11C7/00

    CPC分类号： G11C11/40603 ,  G11C7/22 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2281 ,  G11C2211/4061

    摘要： A timer measures a predetermined time from the reception of an external access signal, and outputs an access request signal after the predetermined time has elapsed. The external access signal causes a memory core to execute a read operation, and the access request signal causes the memory core to operate. The predetermined time is set to be longer than a core operation time for the memory core to perform a single operation. The memory core thus performs no operation when the external access signal varies in a time shorter than the predetermined time. Consequently, it is possible to prevent the memory core from malfunctioning and data retained therein from crashing even when external access signals are supplied at intervals at which the memory core is unable to properly operate.

    摘要翻译： 定时器从接收外部接入信号测量预定时间，并且在经过预定时间之后输出接入请求信号。 外部访问信号使存储器核心执行读取操作，并且访问请求信号使得存储器核心操作。 预定时间被设定为比存储器芯执行单次操作的核心操作时间长。 因此，当外部访问信号在比预定时间短的时间内变化时，存储器核不执行操作。 因此，即使当存储器核心不能正常操作的间隔提供外部访问信号时，也可以防止存储器芯故障并保留其中的数据崩溃。

    Photocatalytic coating film and method for producing same
    38.
    发明授权
    Photocatalytic coating film and method for producing same 有权
    光催化涂膜及其制备方法

    公开(公告)号：US09517459B2

    公开(公告)日：2016-12-13

    申请号：US14124292

    申请日：2012-06-06

    申请人： Toru Nakai ,  Yoshinori Funaki ,  Toshikazu Nakamura

    发明人： Toru Nakai ,  Yoshinori Funaki ,  Toshikazu Nakamura

    IPC分类号： B01J31/38 ,  B01J37/02 ,  B01J35/00 ,  G02B27/00 ,  B01J23/745 ,  B01J21/06 ,  B01J35/06

    CPC分类号： B01J31/38 ,  B01J21/063 ,  B01J23/745 ,  B01J35/004 ,  B01J35/06 ,  B01J37/0215 ,  B01J37/0219 ,  G02B1/18 ,  G02B27/0006

    摘要： Provided is a photocatalytic coating film that can develop excellent photocatalytic activity and exhibit superior adhesion to an adherend surface.The photocatalytic coating film is obtained by applying and drying a photocatalytic coating composition containing at least rod-like or needle-like titanium oxide particles and a binder component so that the photocatalytic coating film contains the titanium oxide particles in a content of 0.5 g/m2 or more. The photocatalytic coating film contains the titanium oxide particle in a content per unit volume (1 m2 by 1 μm thick) of less than 3.0 g. The titanium oxide particles preferably have an aspect ratio of 1.5 or more, the aspect ratio specified as the ratio of a long side length to a short side length of particle. The compositional ratio (by weight) of the titanium oxide particles to the binder component in the photocatalytic coating film is preferably from 1:6 to 30:1.

    摘要翻译： 通过涂布和干燥含有至少棒状或针状二氧化钛颗粒和粘合剂成分的光催化涂料组合物，使得光催化涂膜含有0.5g / m 2的氧化钛颗粒，得到光催化涂膜 或者更多。 光催化涂膜含有小于3.0g的每单位体积（1m 2×1μm）的氧化钛粒子。 优选氧化钛粒子的纵横比为1.5以上，纵横比规定为长边长与粒子的短边长的比例。 光催化性涂膜中的氧化钛粒子与粘合剂成分的组成比（重量比）优选为1:6〜30:1。

    Remote operation apparatus of working machine
    39.
    发明授权
    Remote operation apparatus of working machine 有权
    工作机远程操作装置

    公开(公告)号：US08922343B2

    公开(公告)日：2014-12-30

    申请号：US12775722

    申请日：2010-05-07

    申请人： Toshinori Inagawa ,  Toshikazu Nakamura

    发明人： Toshinori Inagawa ,  Toshikazu Nakamura

    IPC分类号： G08C19/16 ,  G08C17/00

    CPC分类号： G08C17/00 ,  G08C2201/10 ,  G08C2201/12 ,  G08C2201/50

    摘要： In a remote operation apparatus of a working machine including a working machine side transmission/reception unit (21) and a radio remote operation means (3) having a remote control side transmission/reception unit (31), an ON/OFF control circuit (32) for controlling the operation/non-operation state of the remote control side transmission/reception unit (31) is disposed to the radio remote operation means (3), and the working machine side transmission/reception unit (21) is called when the remote control side transmission/reception unit (31) is in an operating state by that the ON/OFF control circuit (32) is turned on, and the data showing the driving state of the working machine (1) is transmitted from the working machine side transmission/reception unit (21) to the remote control side transmission/reception unit (31) to thereby reduce an electric power consumption amount on the radio remote operation means (3).

    摘要翻译： 在具有工作机侧发送接收单元（21）的工作机的远程操作装置和具有遥控侧发送接收单元（31）的无线遥控单元（3）的ON / OFF控制电路（ 32）用于控制遥控器侧发送/接收单元（31）的操作/非操作状态设置在无线电远程操作装置（3）上，并且当工作机侧发送/接收单元（21）被调用时 远程控制侧发送/接收单元（31）处于操作状态，ON / OFF控制电路（32）接通，并且显示工作机（1）的驱动状态的数据从工作 机侧发送接收部（21）发送到遥控侧发送接收部（31），能够减少无线遥控装置（3）的电力消耗量。