公开(公告)号：US20230410873A1

公开(公告)日：2023-12-21

申请号：US18456152

申请日：2023-08-25

Applicant: Micron Technology, Inc.

Inventor： David Hulton ,  Jeremy Chritz ,  Jonathan D. Harms

IPC: G11C11/406 ,  G06F11/07 ,  G06F16/2458 ,  G11C11/4096

CPC classification number: G11C11/406 ,  G06F11/073 ,  G06F11/076 ,  G06F16/2465 ,  G11C11/4096 ,  G06F11/0787 ,  G06F2216/03 ,  G06Q20/0655

Abstract: Methods and apparatus for utilizing non-traditional (e.g., probabilistic or statistically-based) refresh schemes in non-volatile memory. In one embodiment, the memory is characterized in terms of its performance, such as based on BER (bit error rate) as a function of refresh rate based on statistical data for decay of capacitance within the cells of the device with time. In one variant, error-tolerant applications make use of the non-traditionally refreshed (or unrefreshed) memory with enhanced memory bandwidth, since refresh operations have been reduced or eliminated. In another variant, an extant refresh scheme is modified based on a specified minimum allowable performance level for the memory device, In yet another embodiment, error-intolerant applications operate the memory with a reduced or eliminated refresh, and cells or regions of the memory not adequately refreshed by presumed random read/write operations of the memory over time are actively refreshed.

公开(公告)号：US20230334152A1

公开(公告)日：2023-10-19

申请号：US17659409

申请日：2022-04-15

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  David Hulton ,  Jeremy Chritz ,  Tamara Schmitz ,  Max S. Vohra

IPC: G06F21/55 ,  G01K3/00 ,  G01K1/02

CPC classification number: G06F21/554 ,  G01K3/005 ,  G01K1/026

Abstract: Methods, systems, and devices for temperature change measurement to detect an attack on a memory device are described. A memory device may measure a rate of change for temperature readings at a dynamic random access memory (DRAM) component of the memory device (e.g., using sensors at the DRAM component). The memory device may compare the rate of change for the temperature to a threshold, for example, using circuitry, a threshold value stored in memory, or both. If the memory device determines that the rate of change for the temperature satisfies the threshold, the memory device may disable one or more features of the memory device to protect against a potential attack. For example, an attack on the memory device may be indicated by the change in temperature readings at the DRAM component, and the memory device may perform one or more protective measures based on detecting the temperature change.

公开(公告)号：US20230205874A1

公开(公告)日：2023-06-29

申请号：US17653265

申请日：2022-03-02

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  David Hulton ,  Jeremy Chritz ,  Tamara Schmitz ,  Max S. Vohra

IPC: G06F21/55

CPC classification number: G06F21/554 ,  G06F2221/034

Abstract: Methods, systems, and devices for voltage input and clock speed change determination to detect an attack are described. In some systems, a memory device may receive first signaling indicative of a first value for an input (e.g., voltage input, clock speed) to the memory device. The memory device may further receive second signaling indicative of a second (e.g., time-delayed) value for the input to the memory device. The memory device may detect a change to the input based on the first signaling and the second signaling. For example, the memory device may compare the first signaling to the second signaling, may compare a difference between the first signaling and the second signaling to a threshold, or both. If the input changes (e.g., by a threshold amount), the memory device may disable one or more features to protect against an attack on the memory device.

公开(公告)号：US11537298B2

公开(公告)日：2022-12-27

申请号：US17108904

申请日：2020-12-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeremy Chritz ,  David Hulton

IPC: G06F3/06 ,  G06F12/0877 ,  H04L9/06

Abstract: Examples of systems and method described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and/or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.

公开(公告)号：US20220351770A1

公开(公告)日：2022-11-03

申请号：US17867124

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Jonathan D. Harms ,  David Hulton ,  Jeremy Chritz

IPC: G11C11/406 ,  G06F11/10 ,  G11C29/02 ,  G11C29/52

Abstract: Methods and apparatus for dynamically adjusting performance of partitioned memory. In one embodiment, the method includes receiving one or more configuration requests for the memory device, determining whether to grant the one or more configuration requests for the memory device, in response to the determining, implementing the one or more configuration requests within the memory device and operating the memory device in accordance with the implementing. The adjusting of the performance for the partitioned memory includes one or more of enabling/disabling refresh operations, altering a refresh rate for the partitioned memory, enabling/disabling error correcting code (ECC) circuitry for the partitioned memory, and/or altering a memory cell architecture for the partitioned memory. Systems and applications that may benefit from the dynamic adjustment of performance are also disclosed.

公开(公告)号：US11341057B2

公开(公告)日：2022-05-24

申请号：US17068370

申请日：2020-10-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeremy Chritz ,  David Hulton

IPC: G06F12/10 ,  G06F3/06

Abstract: Apparatuses and methods for managing a coherent memory are described. These may include one or more algorithmic logic units (ALUs) and an input/output (I/O) interface. The I/O interface may receive one or more commands and retrieve data from or write data to a memory device. Each command may contain a memory address portion associated with a memory device. The apparatus may also include a memory mapping unit and a device controller. The memory mapping unit may map the memory address to a memory portion of the memory device, and the device controller may communicate with the memory device to retrieve data from or write data to the memory device. The apparatus may be implemented as a processing element in a configurable logic block network, which may additionally include a control logic unit that receives programming instructions from an application and generate the one or more commands based on the instructions.

公开(公告)号：US11183266B2

公开(公告)日：2021-11-23

申请号：US16453905

申请日：2019-06-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David Hulton ,  Tamara Schmitz ,  Jonathan D. Harms ,  Jeremy Chritz ,  Kevin Majerus

IPC: G11C29/00 ,  G06F12/126 ,  G06F12/02 ,  G06F3/06 ,  G11C29/04 ,  G06F12/0813 ,  G11C29/44 ,  H04L29/12 ,  G06F11/10 ,  G11C11/408 ,  G11C11/418

Abstract: Methods, apparatuses, and systems for repairing defective memory cells in regions of a memory array associated with high or low priority levels are disclosed. A repair address generator may be configured to generate a memory address map for repair (e.g., blowing fuses at a fuse circuit), depending on whether certain applications may operate at a high priority level indicative of a low bit error rate or a low priority level indicative of a higher bit error rate. For example, a specified error rate associated with a low priority level may correspond to a threshold error rate for certain applications, such as a neural network application that stores trained weights. Such neural network applications may access trained weights being partially stored in defective memory cells, with the least significant bits of such trained weights being stored in defective memory cells that are not repaired according to the memory address map.

公开(公告)号：US11061674B2

公开(公告)日：2021-07-13

申请号：US15726293

申请日：2017-10-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gregory Edvenson ,  David Hulton ,  Jeremy Chritz

IPC: G06F9/38 ,  G06F15/78 ,  G06F15/80 ,  G06F9/30 ,  G06N20/00

Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include configurable logic blocks including DSP slices and an interconnected coupling the configurable logic blocks. An operand register of a DSP slice may include an operand input that is coupled to an output of that DSP slice.

公开(公告)号：US11003448B2

公开(公告)日：2021-05-11

申请号：US16116869

申请日：2018-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gregory Edvenson ,  David Hulton ,  Jeremy Chritz

IPC: G06F15/76 ,  G06F15/80 ,  G06F9/30 ,  G06N20/00 ,  G06F15/78 ,  G06F9/38

Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include configurable logic blocks including DSP slices and an interconnected coupling the configurable logic blocks. An operand register of a DSP slice may include an operand input that is coupled to an output of that DSP slice.

公开(公告)号：US20210098047A1

公开(公告)日：2021-04-01

申请号：US17121466

申请日：2020-12-14

Applicant: Micron Technology, Inc.

Inventor： Jonathan D. Harms ,  David Hulton ,  Jeremy Chritz

IPC: G11C11/406 ,  G06F11/10 ,  G11C29/02 ,  G11C29/52

Abstract: Methods and apparatus for dynamically adjusting performance of partitioned memory. In one embodiment, the method includes receiving one or more configuration requests for the memory device, determining whether to grant the one or more configuration requests for the memory device, in response to the determining, implementing the one or more configuration requests within the memory device and operating the memory device in accordance with the implementing. The adjusting of the performance for the partitioned memory includes one or more of enabling/disabling refresh operations, altering a refresh rate for the partitioned memory, enabling/disabling error correcting code (ECC) circuity for the partitioned memory, and/or altering a memory cell architecture for the partitioned memory. Systems and applications that may benefit from the dynamic adjustment of performance are also disclosed.