公开(公告)号：US20210208964A1

公开(公告)日：2021-07-08

申请号：US17211280

申请日：2021-03-24

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G06F11/10 ,  G06F11/07 ,  G11C16/24 ,  G11C16/26

Abstract: Methods, systems, and devices for spare substitution in a memory system are described. A controller may, as part of a background operation, assign a spare bit to replace a bit of a code word and save an indication of the spare bit assignment in a memory array. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) within a memory medium that retains the code word. An MSR corresponding to the bit to be replaced may include a quantity of erroneous bits relative to a threshold. The controller may, during a read operation, identify the spare bit in a first portion of the code word, determine the bit to be replaced based on accessing the memory array, and replace the bit with the spare bit concurrently with receiving a second portion of the code word.

公开(公告)号：US20200034225A1

公开(公告)日：2020-01-30

申请号：US16516897

申请日：2019-07-19

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G06F11/10 ,  G11C11/409

Abstract: Methods, systems, and devices for erroneous bit discovery in a memory system are described. A controller or memory controller, for example, may read a code word from a memory medium. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) of the memory medium. Each MSR may include a portion of memory cells of the memory medium and be associated with a counter to count a quantity of erroneous bits in each MSR. When the controller identifies a quantity of erroneous bits in the code word using an error control operation, the controller may update values of counters associated with respective MSRs that correspond to the quantity of erroneous bits to count erroneous bit counts for each MSR. In some cases, the controller may perform operations described herein as part of a background operation.

公开(公告)号：US11886338B2

公开(公告)日：2024-01-30

申请号：US17861018

申请日：2022-07-08

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G06F12/06 ,  G06F11/10

CPC classification number: G06F12/0646 ,  G06F11/1076 ,  G06F2212/1032

Abstract: Methods, systems, and devices for forwarding a code word address are described. A memory subsystem, for example, may configure a code word including user data as a forwarded code word when the code word becomes unreliable or invalid close to or beyond an error recovery capability of the memory subsystem. The memory subsystem may configure the forwarded code word using a forwarded code word format and structure, which may include a bit field in the forwarded code word to indicate a code word condition and to store a quantity of duplicates of a forwarding address. When the memory subsystem receives a code word, the memory system may determine the code word as a forwarded code word such that the memory system may determine a forwarding address (e.g., from the code word). The memory subsystem may then use the forwarding address to access user data.

公开(公告)号：US11720502B2

公开(公告)日：2023-08-08

申请号：US17468160

申请日：2021-09-07

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G06F12/12 ,  G06F12/0804 ,  H03M13/27 ,  H03M13/00 ,  G06F12/0891

CPC classification number: G06F12/12 ,  G06F12/0804 ,  G06F12/0891 ,  H03M13/2782 ,  H03M13/6563 ,  H03M13/6566

Abstract: Methods, systems, and devices for codeword rotation for zone grouping of media codewords are described. A value of a first pointer may be configured to correspond to a first memory address within a region of memory and a value of a second pointer may be configured to correspond to a second memory address within the region of memory. The method may include monitoring access commands for performing access operations within the region of memory, where the plurality of access command may be associated with requested addresses within the region of memory. The method may include updating the value of the second pointer bases on a quantity of the commands that are monitored satisfying a threshold and executing the plurality of commands on locations within the region of memory. The locations may be based on the requested address, the value of the first pointer, and the value of the second pointer.

公开(公告)号：US20230037229A1

公开(公告)日：2023-02-02

申请号：US17885158

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G06F11/10 ,  G06F11/07 ,  G11C16/24 ,  G11C16/26

Abstract: Methods, systems, and devices for spare substitution in a memory system are described. A controller may, as part of a background operation, assign a spare bit to replace a bit of a code word and save an indication of the spare bit assignment in a memory array. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) within a memory medium that retains the code word. An MSR corresponding to the bit to be replaced may include a quantity of erroneous bits relative to a threshold. The controller may, during a read operation, identify the spare bit in a first portion of the code word, determine the bit to be replaced based on accessing the memory array, and replace the bit with the spare bit concurrently with receiving a second portion of the code word.

公开(公告)号：US20220222180A1

公开(公告)日：2022-07-14

申请号：US17657922

申请日：2022-04-04

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Joseph Thomas Pawlowski

IPC: G06F12/0815 ,  G06F12/0804 ,  G06F12/0864

Abstract: Described apparatuses and methods form adaptive cache lines having a configurable capacity from hardware cache lines having a fixed capacity. The adaptive cache lines can be formed in accordance with a programmable cache-line parameter. The programmable cache-line parameter can specify a capacity for the adaptive cache lines. The adaptive cache lines may be formed by combining respective groups of fixed-capacity hardware cache lines. The quantity of fixed-capacity hardware cache lines included in respective adaptive cache lines may be based on the programmable cache-line parameter. The programmable cache-line parameter can be selected in accordance with characteristics of the cache workload.

公开(公告)号：US20220199130A1

公开(公告)日：2022-06-23

申请号：US17690907

申请日：2022-03-09

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G11C7/10 ,  H04L47/10 ,  G06F13/18 ,  G06F13/16

Abstract: Methods, systems, and devices for a multi-port storage-class memory interface are described. A memory controller of the storage-class memory subsystem may receive, from a host device, a request associated with host addresses. The memory controller may generate interleaved addresses with a low latency based on the host addresses. The interleaved addresses parallelize processing of the request utilizing a set of memory media ports. Each memory media port of the set of memory media port may operate independent of each other to obtain a desired aggregated data transfer rate and a memory capacity. The interleaved address may leave no gaps in memory space. The memory controller may control a wear-leveling operation to distribute access operations across one or more zones of the memory media port.

公开(公告)号：US20220197736A1

公开(公告)日：2022-06-23

申请号：US17690682

申请日：2022-03-09

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G06F11/10 ,  G11C11/409

Abstract: Methods, systems, and devices for erroneous bit discovery in a memory system are described. A controller or memory controller, for example, may read a code word from a memory medium. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) of the memory medium. Each MSR may include a portion of memory cells of the memory medium and be associated with a counter to count a quantity of erroneous bits in each MSR. When the controller identifies a quantity of erroneous bits in the code word using an error control operation, the controller may update values of counters associated with respective MSRs that correspond to the quantity of erroneous bits to count erroneous bit counts for each MSR. In some cases, the controller may perform operations described herein as part of a background operation.

公开(公告)号：US11294808B2

公开(公告)日：2022-04-05

申请号：US16880248

申请日：2020-05-21

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Joseph Thomas Pawlowski

IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/0804 ,  G06F12/0864

Abstract: Described apparatuses and methods form adaptive cache lines having a configurable capacity from hardware cache lines having a fixed capacity. The adaptive cache lines can be formed in accordance with a programmable cache-line parameter. The programmable cache-line parameter can specify a capacity for the adaptive cache lines. The adaptive cache lines may be formed by combining respective groups of fixed-capacity hardware cache lines. The quantity of fixed-capacity hardware cache lines included in respective adaptive cache lines may be based on the programmable cache-line parameter. The programmable cache-line parameter can be selected in accordance with characteristics of the cache workload.

公开(公告)号：US11288118B2

公开(公告)日：2022-03-29

申请号：US16863966

申请日：2020-04-30

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G06F11/00 ,  G06F11/10 ,  G11C11/409

Abstract: Methods, systems, and devices for erroneous bit discovery in a memory system are described. A controller or memory controller, for example, may read a code word from a memory medium. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) of the memory medium. Each MSR may include a portion of memory cells of the memory medium and be associated with a counter to count a quantity of erroneous bits in each MSR. When the controller identifies a quantity of erroneous bits in the code word using an error control operation, the controller may update values of counters associated with respective MSRs that correspond to the quantity of erroneous bits to count erroneous bit counts for each MSR. In some cases, the controller may perform operations described herein as part of a background operation.