公开(公告)号：US11893280B2

公开(公告)日：2024-02-06

申请号：US17459343

申请日：2021-08-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason Duong ,  Fangfang Zhu ,  Jiangli Zhu ,  Juane Li ,  Chih-Kuo Kao

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A system can include a memory device and a processing device coupled with the memory device. The processing device can receive a command of a first type from a host system. The processing device can select a threshold criterion for the command of the first type based on a count of commands of a second type. The processing device can determine whether a second count of commands of the first type satisfies the threshold criterion and in response to the second count satisfying the threshold criterion, the processing logic can transmit a notification to the host system to refrain from transmitting the commands of the first type.

公开(公告)号：US11775216B2

公开(公告)日：2023-10-03

申请号：US17460828

申请日：2021-08-30

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Jiangli Zhu ,  Juane Li

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/064 ,  G06F3/0604 ,  G06F3/0679

Abstract: A system includes a memory device, and a processing device, operatively coupled with the memory device, to perform operations including receiving a media access operation access command to perform a media access operation with respect to a memory location residing on the memory device, determining whether there exists another memory location access at the memory location, in response to determining that another memory location access exists at the memory location, determining whether the media access operation command is a read command, and in response to determining that the media access operation is a read command, servicing the media access operation command from a media buffer. The media buffer maintains data associated with the completed write operation.

公开(公告)号：US11698867B2

公开(公告)日：2023-07-11

申请号：US17458173

申请日：2021-08-26

Applicant: Micron Technology, Inc.

Inventor： Seungjune Jeon ,  Fangfang Zhu ,  Juane Li ,  Jiangli Zhu ,  Ning Chen

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F2212/7201

Abstract: A logical-to-physical (L2P) data structure and a physical-to-logical (P2L) data structure are maintained. The L2P data structure comprises table entries that map a logical address to a physical address. The P2L data structure comprises data entries that map a physical address to a logical address. The P2L data entries also comprise a data move status, a base address, and a boundary indicator. A move operation is detected, wherein the move operation indicates that data referenced by a logical address is to be moved from a source physical address to a destination physical address. Responsive to detecting the move operation, the data move status associated with the source physical address in the P2L data structure is updated.

公开(公告)号：US11615214B2

公开(公告)日：2023-03-28

申请号：US16913748

申请日：2020-06-26

Applicant: Micron Technology, Inc.

Inventor： Juane Li ,  Jiangli Zhu ,  Ying Yu Tai

IPC: G06F21/79 ,  G06F21/60 ,  H04L9/08 ,  G11C29/44 ,  G11C29/42

Abstract: Methods, systems, and devices for cryptographic key management are described. A memory device can issue, by a firmware component, a command to generate a first cryptographic key for encrypting or decrypting user data stored on a memory device. The memory device can generate, by a hardware component, the first cryptographic key based on the command. The memory device can encrypt, by the hardware component, the first cryptographic key using a second cryptographic key and an initialization vector. The memory device can store the encrypted first cryptographic key in a nonvolatile memory device separate from the hardware component.

公开(公告)号：US20230069122A1

公开(公告)日：2023-03-02

申请号：US17458173

申请日：2021-08-26

Applicant: Micron Technology, Inc.

Inventor： Seungjune Jeon ,  Fangfang Zhu ,  Juane Li ,  Jiangli Zhu ,  Ning Chen

IPC: G06F12/1009

Abstract: A logical-to-physical (L2P) data structure and a physical-to-logical (P2L) data structure are maintained. The L2P data structure comprises table entries that map a logical address to a physical address. The P2L data structure comprises data entries that map a physical address to a logical address. The P2L data entries also comprise a data move status, a base address, and a boundary indicator. A move operation is detected, wherein the move operation indicates that data referenced by a logical address is to be moved from a source physical address to a destination physical address. Responsive to detecting the move operation, the data move status associated with the source physical address in the P2L data structure is updated.

公开(公告)号：US20230066863A1

公开(公告)日：2023-03-02

申请号：US17459846

申请日：2021-08-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Juane Li ,  Fangfang Zhu ,  Seungjune Jeon ,  Yueh-Hung Chen

IPC: G06F11/10 ,  G06F11/30 ,  G06F12/02 ,  G06F3/06

Abstract: A request is received to program host data to a memory device of a memory sub-system. The host data is associated with a logical address. A redundancy factor that corresponds to the logical address associated with the host data is obtained. A first physical address associated with a first set of cells of the memory device and a second physical address associated with a second set of cells of the memory device are determined based on the redundancy factor. The first set of memory cells is to store the host data and the second set of memory cells is to store redundancy metadata associated with the host data. The host data is programmed to the first set of memory cells. The redundancy metadata associated with the host data is programmed to the second set of memory cells.

公开(公告)号：US20230064382A1

公开(公告)日：2023-03-02

申请号：US17460972

申请日：2021-08-30

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Jiangli Zhu ,  Juane Li

IPC: G06F3/06

Abstract: A system includes a processing device, operatively coupled with a memory device, to perform operations including receiving a media access operation command designating a first memory location, and determining whether a first media access operation command designating the first memory location and a second media access operation designating a second memory location are synchronized, after determining that the first and second media access operation commands are not synchronized, determining that the media access operation command is an error flow recovery (ERF) read command, in response to determining that the media access operation command is an ERF read command, determining whether a head command of the first queue is blocked from execution, and in response to determining that the head command is unblocked from execution, servicing the ERF read command from a media buffer maintaining previously written ERF data.

公开(公告)号：US20230064282A1

公开(公告)日：2023-03-02

申请号：US17460828

申请日：2021-08-30

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Jiangli Zhu ,  Juane Li

IPC: G06F3/06

Abstract: A system includes a memory device, and a processing device, operatively coupled with the memory device, to perform operations including receiving a media access operation access command to perform a media access operation with respect to a memory location residing on the memory device, determining whether there exists another memory location access at the memory location, in response to determining that another memory location access exists at the memory location, determining whether the media access operation command is a read command, and in response to determining that the media access operation is a read command, servicing the media access operation command from a media buffer. The media buffer maintains data associated with the completed write operation.

公开(公告)号：US20230064168A1

公开(公告)日：2023-03-02

申请号：US17459343

申请日：2021-08-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason Duong ,  Fangfang Zhu ,  Jiangli Zhu ,  Juane Li ,  Chih-Kuo Kao

IPC: G06F3/06

Abstract: A system can include a memory device and a processing device coupled with the memory device. The processing device can receive a command of a first type from a host system. The processing device can select a threshold criterion for the command of the first type based on a count of commands of a second type. The processing device can determine whether a second count of commands of the first type satisfies the threshold criterion and in response to the second count satisfying the threshold criterion, the processing logic can transmit a notification to the host system to refrain from transmitting the commands of the first type.

公开(公告)号：US20210019450A1

公开(公告)日：2021-01-21

申请号：US16913748

申请日：2020-06-26

Applicant: Micron Technology, Inc.

Inventor： Juane Li ,  Jiangli Zhu ,  Ying Yu Tai

IPC: G06F21/79 ,  G06F21/60 ,  H04L9/08 ,  G11C29/42 ,  G11C29/44

Abstract: Methods, systems, and devices for cryptographic key management are described. A memory device can issue, by a firmware component, a command to generate a first cryptographic key for encrypting or decrypting user data stored on a memory device. The memory device can generate, by a hardware component, the first cryptographic key based on the command. The memory device can encrypt, by the hardware component, the first cryptographic key using a second cryptographic key and an initialization vector. The memory device can store the encrypted first cryptographic key in a nonvolatile memory device separate from the hardware component.