公开(公告)号：US20210375670A1

公开(公告)日：2021-12-02

申请号：US17444948

申请日：2021-08-12

Applicant: Micron Technology, Inc.

Inventor： Xiaosong Zhang ,  Yongjun J. Hu ,  David A. Kewley ,  Md Zahid Hossain ,  Michael J. Irwin ,  Daniel Billingsley ,  Suresh Ramarajan ,  Robert J. Hanson ,  Biow Hiem Ong ,  Keen Wah Chow

IPC: H01L21/768

Abstract: An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.

公开(公告)号：US20210263429A1

公开(公告)日：2021-08-26

申请号：US17314410

申请日：2021-05-07

Applicant: Micron Technology, Inc.

Inventor： Nikolay A. Mirin ,  Robert Dembi ,  Richard T. Housley ,  Xiaosong Zhang ,  Jonathan D. Harms ,  Stephen J. Kramer

IPC: G03F7/20 ,  H01L21/68 ,  G01R33/07 ,  H01L23/544

Abstract: A method of aligning a wafer for semiconductor fabrication processes may include applying a magnetic field to a wafer, detecting one or more residual magnetic fields from one or more alignment markers within the wafer, responsive to the detected one or more residual magnetic fields, determining locations of the one or more alignment markers. The marker locations may be determined relative to an ideal grid, followed by determining a geometrical transformation model for aligning the wafer, and aligning the wafer responsive to the geometrical transformation model. Related methods and systems are also disclosed.

公开(公告)号：US20210057349A1

公开(公告)日：2021-02-25

申请号：US16546759

申请日：2019-08-21

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Harsh Narendrakumar Jain ,  John D. Hopkins ,  Xiaosong Zhang

IPC: H01L23/544

Abstract: An electronic device comprising at least one high aspect ratio feature in a base stack of materials, overlay marks in or on only an upper portion of the base stack of materials, and an additional stack of materials adjacent the base stack of materials, the additional stack of materials comprising the at least one high aspect ratio feature. Additional electronic devices and memory devices are disclosed, as are methods of forming high aspect ratio features in an electronic device.

公开(公告)号：US20200075432A1

公开(公告)日：2020-03-05

申请号：US16122106

申请日：2018-09-05

Applicant: Micron Technology, Inc.

Inventor： Nikolay A. Mirin ,  Robert Dembi ,  Richard T. Housley ,  Xiaosong Zhang ,  Jonathan D. Harms ,  Stephen J. Kramer

IPC: H01L21/66 ,  H01L23/544 ,  H01L21/68 ,  H01L21/302

Abstract: A method for measuring overlay between an interest level and a reference level of a wafer includes applying a magnetic field to a wafer, detecting at least one residual magnetic field emitted from at least one registration marker of a first set of registration markers within the wafer, responsive to the detected one or more residual magnetic fields, determining a location of the at least one registration marker of the first set registration markers, determining a location of at least one registration marker of a second set of registration markers, and responsive to the respective determined locations of the at least one registration marker of the first set of registration markers and the at least one registration marker of the second set of registration markers, calculating a positional offset between an interest level of the wafer and a reference level of the wafer. Related methods and systems are also disclosed.