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公开(公告)号:US20240074153A1
公开(公告)日:2024-02-29
申请号:US17896039
申请日:2022-08-25
Applicant: Micron Technology, Inc.
Inventor: Daniel Billingsley , Jaydip Guha , Marko Milojevic , Sau Ha Cheung , Luca Fumagalli
IPC: H01L27/108 , H01B1/02
CPC classification number: H01L27/10823 , H01B1/02 , H01L27/10876
Abstract: Methods, apparatuses, and systems related to conductive structures are described. An example conductive structure includes a first conductive material including a conductive metal nitride, where the first conductive material has a thickness of at least 0.5 nanometers, and a second conductive material including a conductive metal, where the second conductive material is disposed on a first surface of the first conductive material.
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公开(公告)号:US20220415917A1
公开(公告)日:2022-12-29
申请号:US17822708
申请日:2022-08-26
Applicant: Micron Technology, Inc.
Inventor: Daniel Billingsley , Matthew J. King , Jordan D. Greenlee , Yongjun J. Hu , Tom George , Amritesh Rai , Sidhartha Gupta , Kyle A. Ritter
IPC: H01L27/11573 , H01L27/11582 , H01L27/11556 , H01L21/28 , H01L29/49 , H01L27/11529
Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.
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3.
公开(公告)号:US11205654B2
公开(公告)日:2021-12-21
申请号:US16550238
申请日:2019-08-25
Applicant: Micron Technology, Inc.
Inventor: Yi Hu , Ramey M. Abdelrahaman , Narula Bilik , Daniel Billingsley , Zhenyu Bo , Joan M. Kash , Matthew J. King , Andrew Li , David Neumeyer , Wei Yeeng Ng , Yung K. Pak , Chandra Tiwari , Yiping Wang , Lance Williamson , Xiaosong Zhang
IPC: H01L27/11556 , H01L27/11524 , H01L27/11582 , H01L27/1157
Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.
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公开(公告)号:US20190355711A1
公开(公告)日:2019-11-21
申请号:US16398433
申请日:2019-04-30
Applicant: Micron Technology, Inc.
Inventor: Daniel Billingsley , Everett A. McTeer , Christopher W. Petz , Haoyu Li , John Mark Meldrim , Yongjun Jeff Hu
Abstract: An integrated assembly includes an insulative mass with a first region adjacent to a second region. The first region has a greater amount of one or more inert interstitial elements incorporated therein than does the second region. Some embodiments include an integrated assembly which has vertically-extending channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure includes doped semiconductor material in direct contact with bottom regions of the channel material pillars. An insulative mass is along the bottom regions of the channel material pillars. The insulative mass has an upper region over a lower region. The lower region has a greater amount of one or more inert interstitial elements incorporated therein than does the upper region. Some embodiments include methods of forming integrated assemblies.
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公开(公告)号:US20190304996A1
公开(公告)日:2019-10-03
申请号:US16431527
申请日:2019-06-04
Applicant: Micron Technology, Inc.
Inventor: David Ross Economy , John Mark Meldrim , Haoyu Li , Yongjun Jeff Hu , Christopher W. Petz , Daniel Billingsley , Everett A. McTeer
IPC: H01L27/11582 , H01L21/768 , H01L27/11565 , H01L27/11556 , H01L27/11519 , H01L21/311
Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.
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公开(公告)号:US20190198519A1
公开(公告)日:2019-06-27
申请号:US15852989
申请日:2017-12-22
Applicant: Micron Technology, Inc.
Inventor: David Ross Economy , John Mark Meldrim , Haoyu Li , Yongjun Jeff Hu , Christopher W. Petz , Daniel Billingsley , Everett A. McTeer
IPC: H01L27/11582 , H01L27/11556 , H01L21/768 , H01L21/311 , H01L27/11565 , H01L27/11519
CPC classification number: H01L27/11582 , H01L21/31144 , H01L21/76831 , H01L27/11519 , H01L27/11556 , H01L27/11565
Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.
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公开(公告)号:US11990367B2
公开(公告)日:2024-05-21
申请号:US17444948
申请日:2021-08-12
Applicant: Micron Technology, Inc.
Inventor: Xiaosong Zhang , Yongjun J. Hu , David A. Kewley , Md Zahid Hossain , Michael J. Irwin , Daniel Billingsley , Suresh Ramarajan , Robert J. Hanson , Biow Hiem Ong , Keen Wah Chow
IPC: H01L21/768
CPC classification number: H01L21/76831 , H01L21/76843 , H01L21/76879 , H01L21/76804
Abstract: An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.
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公开(公告)号:US11792983B2
公开(公告)日:2023-10-17
申请号:US17068430
申请日:2020-10-12
Applicant: Micron Technology, Inc.
Inventor: Daniel Billingsley , Jordan D. Greenlee , John D. Hopkins , Yongjun Jeff Hu , Swapnil Lengade
IPC: H01L21/31 , H10B43/27 , H01L21/311 , H10B41/27
CPC classification number: H10B43/27 , H01L21/31111 , H10B41/27
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lowers-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-first-tiers or a lower of the upper-first-tiers comprises non-stoichiometric silicon nitride comprising (a) or (b), where (a): a nitrogen-to-silicon atomic ratio greater than 1.33 and less than 1.5; and (b): a nitrogen-to-silicon atomic ratio greater than or equal to 1.0 and less than 1.33. A higher of the upper-first-tiers that is above said lower upper-first-tier comprises silicon nitride not having either the (a) or the (b). Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-first-tier or said lower upper-first-tier. After the stop, the sacrificial material is removed from the lower channel openings and form channel-material strings in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.
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公开(公告)号:US20220238444A1
公开(公告)日:2022-07-28
申请号:US17658907
申请日:2022-04-12
Applicant: Micron Technology, Inc.
Inventor: Jordan D. Greenlee , John D. Hopkins , Rita J. Klein , Everett A. McTeer , Lifang Xu , Daniel Billingsley , Collin Howder
IPC: H01L23/535 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L21/768 , H01L23/528 , H01L23/532 , H01L23/522
Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
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10.
公开(公告)号:US20220059569A1
公开(公告)日:2022-02-24
申请号:US17517459
申请日:2021-11-02
Applicant: Micron Technology, Inc.
Inventor: Jordan D. Greenlee , Daniel Billingsley , Indra V. Chary , Rita J. Klein
IPC: H01L27/11582 , H01L27/11556 , H01L21/02 , H01L21/311 , H01L27/11519 , H01L27/11565
Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Upper masses comprise first material laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks and second material laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory blocks longitudinally-between and under the upper masses. The second material is of different composition from that of the first material. The second material comprises insulative material. Other embodiments, including method, are disclosed.
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