公开(公告)号：US11158652B1

公开(公告)日：2021-10-26

申请号：US17346295

申请日：2021-06-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: G11C16/04 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  G11C7/18 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11529

Abstract: A 3D memory device, the device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented, and where the channel is isolated from another channel disposed directly above the channel.

公开(公告)号：US11018156B2

公开(公告)日：2021-05-25

申请号：US17099706

申请日：2020-11-16

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: G11C16/04 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  G11C7/18 ,  H01L27/11565

Abstract: A 3D memory device, the device including: a plurality of memory cells, where each of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source and a drain; a plurality of bit-line pillars, where each of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where each of the plurality of bit-line pillars includes metal atoms such that the plurality of bit-line pillars have at least partial metallic properties; and a thermal path from the bit-line pillars to an external surface of the device to remove heat. Various 3D processing flows and methods are also disclosed.

公开(公告)号：US12021067B2

公开(公告)日：2024-06-25

申请号：US18389752

申请日：2023-12-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist ,  Eli Lusky

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/473 ,  H01L23/48 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L23/473 ,  H01L23/481 ,  H01L24/08 ,  H10B80/00 ,  H01L2224/08146 ,  H01L2225/06544 ,  H01L2924/1421 ,  H01L2924/1431

Abstract: A 3D device, the device including: at least one first level including logic circuits; at least one second level bonded to the first level, where the at least one second level includes a plurality of transistors; connectivity structures, where the connectivity structures include a plurality of transmission lines, where the plurality of transmission lines are designed to conduct radio frequencies (“RF”) signals, and where the bonded includes oxide to oxide bond regions and metal to metal bond regions; and a plurality of vias disposed through the at least one second level, where at least a majority of the plurality of vias have a diameter of less than 5 micrometers.

公开(公告)号：US20220189990A1

公开(公告)日：2022-06-16

申请号：US17681767

申请日：2022-02-26

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: H01L27/11582 ,  H01L23/522

Abstract: A 3D memory device, the device comprising: a plurality of memory cells, wherein each memory cell of said plurality of memory cells comprises at least one memory transistor, wherein each of said at least one memory transistor comprises a source, a drain, and a channel; a plurality of bit-line pillars, wherein each bit-line pillar of said plurality of bit-line pillars is directly connected to a plurality of said source or said drain, wherein said bit-line pillars are vertically oriented, wherein said channel is horizontally oriented, wherein said plurality of memory cells comprise a partially or fully metalized source, and/or, a partially or fully metalized drain, and wherein said plurality of bit-line pillars comprise a thermally conductive path from said plurality of memory cells to an external surface of said device.

公开(公告)号：US20220013533A1

公开(公告)日：2022-01-13

申请号：US17484394

申请日：2021-09-24

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: H01L27/11578 ,  H01L27/11573

Abstract: A 3D memory device, the device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented; and a level of memory control circuits, where the memory control circuits is disposed either above or below the plurality of memory cells.

公开(公告)号：US11152386B2

公开(公告)日：2021-10-19

申请号：US16483431

申请日：2018-02-03

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: H01L29/76 ,  H01L27/11556 ,  H01L21/28 ,  H01L27/11582 ,  H01L29/423

Abstract: A 3D memory device, the device including: a first vertical pillar; a second vertical pillar, where the first vertical pillar and the second vertical pillar function as a source or a drain for a plurality of overlaying horizontally-oriented memory transistors, where the plurality of overlaying horizontally-oriented memory transistors are self-aligned being formed following the same lithography step; and memory control circuits, where the memory control circuits are disposed at least partially directly underneath the plurality of overlaying horizontally-oriented memory transistors, or are disposed at least partially directly above the plurality of overlaying horizontally-oriented memory transistors.

公开(公告)号：US20210313345A1

公开(公告)日：2021-10-07

申请号：US17346295

申请日：2021-06-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  G11C7/18

Abstract: A 3D memory device, the device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented, and where the channel is isolated from another channel disposed directly above the channel.