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公开(公告)号：US11138009B2
公开(公告)日：2021-10-05
申请号：US16101247
申请日：2018-08-10
Applicant: NVIDIA Corporation
Inventor： Ronald Charles Babich, Jr. , John Burgess , Jack Choquette , Tero Karras , Samuli Laine , Ignacio Llamas , Gregory Muthler , William Parsons Newhall, Jr.
Abstract: Systems and methods for an efficient and robust multiprocessor-coprocessor interface that may be used between a streaming multiprocessor and an acceleration coprocessor in a GPU are provided. According to an example implementation, in order to perform an acceleration of a particular operation using the coprocessor, the multiprocessor: issues a series of write instructions to write input data for the operation into coprocessor-accessible storage locations, issues an operation instruction to cause the coprocessor to execute the particular operation; and then issues a series of read instructions to read result data of the operation from coprocessor-accessible storage locations to multiprocessor-accessible storage locations.
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公开(公告)号：US10825230B2
公开(公告)日：2020-11-03
申请号：US16101148
申请日：2018-08-10
Applicant: NVIDIA Corporation
Inventor： Samuli Laine , Tero Karras , Timo Aila , Robert Ohannessian , William Parsons Newhall, Jr. , Greg Muthler , Ian Kwong , Peter Nelson , John Burgess
Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to properly handle numerically challenging computations at or near edges and/or vertices of primitives and/or ensure that a single intersection is reported when a ray intersects a surface formed by primitives at or near edges and/or vertices of the primitives.
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公开(公告)号：US12198253B2
公开(公告)日：2025-01-14
申请号：US18239876
申请日：2023-08-30
Applicant: NVIDIA Corporation
Inventor： Samuli Laine , Tero Karras , Greg Muthler , William Parsons Newhall, Jr. , Ronald Charles Babich, Jr. , Ignacio Llamas , John Burgess
Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to provide a deterministic result of intersected triangles regardless of the order that the memory subsystem returns triangle range blocks for processing, while opportunistically eliminating alpha intersections that lie further along the length of the ray than closer opaque intersections.
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公开(公告)号：US12198252B2
公开(公告)日：2025-01-14
申请号：US17946193
申请日：2022-09-16
Applicant: NVIDIA Corporation
Inventor： Gregory Muthler , John Burgess , Magnus Andersson , Ian Kwong , Edward Biddulph
Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
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公开(公告)号：US12198251B2
公开(公告)日：2025-01-14
申请号：US17946093
申请日：2022-09-16
Applicant: NVIDIA Corporation
Inventor： Gregory Muthler , John Burgess , Magnus Andersson , Ian Kwong , Edward Biddulph
Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
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Patent Agency Ranking
公开(公告)号：US11966737B2
公开(公告)日：2024-04-23
申请号：US17465234
申请日：2021-09-02
Applicant: NVIDIA Corporation
Inventor： Ronald Charles Babich, Jr. , John Burgess , Jack Choquette , Tero Karras , Samuli Laine , Ignacio Llamas , Gregory Muthler , William Parsons Newhall, Jr.
CPC classification number: G06F9/3004 , G06F9/3877 , G06F9/4843 , G06F15/163 , G06T1/20 , G06T1/60 , G06T2200/28
Abstract: Systems and methods for an efficient and robust multiprocessor-coprocessor interface that may be used between a streaming multiprocessor and an acceleration coprocessor in a GPU are provided. According to an example implementation, in order to perform an acceleration of a particular operation using the coprocessor, the multiprocessor: issues a series of write instructions to write input data for the operation into coprocessor-accessible storage locations, issues an operation instruction to cause the coprocessor to execute the particular operation; and then issues a series of read instructions to read result data of the operation from coprocessor-accessible storage locations to multiprocessor-accessible storage locations.
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公开(公告)号：US11854141B2
公开(公告)日：2023-12-26
申请号：US17968485
申请日：2022-10-18
Applicant: NVIDIA Corporation
Inventor： Gregory Muthler , John Burgess , Ronald Charles Babich, Jr. , William Parsons Newhall, Jr.
CPC classification number: G06T15/06 , G06F9/48 , G06F9/5027 , G06T17/10 , G06T2210/21
Abstract: Techniques are disclosed for improving the throughput of ray intersection or visibility queries performed by a ray tracing hardware accelerator. Throughput is improved, for example, by releasing allocated resources before ray visibility query results are reported by the hardware accelerator. The allocated resources are released when the ray visibility query results can be stored in a compressed format outside of the allocated resources. When reporting the ray visibility query results, the results are reconstructed based on the results stored in the compressed format. The compressed format storage can be used for ray visibility queries that return no intersections or terminate on any hit ray visibility query. One or more individual components of allocated resources can also be independently deallocated based on the type of data to be returned and/or results of the ray visibility query.
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公开(公告)号：US11804002B2
公开(公告)日：2023-10-31
申请号：US17689268
申请日：2022-03-08
Applicant: NVIDIA Corporation
Inventor： Gregory Muthler , John Burgess
CPC classification number: G06T15/06 , G06N3/02 , G06T15/005
Abstract: Ray tracing hardware accelerators supporting multiple specifiers for controlling the traversal of a ray tracing acceleration data structure are disclosed. For example, traversal efficiency and complex ray tracing effects can be achieved by specifying traversals through such data structures using both programmable ray operations and explicit node masking. The explicit node masking utilizes dedicated fields in the ray and in nodes of the acceleration data structure to control traversals. Ray operations, however, are programmable per ray using opcodes and additional parameters to control traversals. Traversal efficiency is improved by enabling more aggressive culling of parts of the data structure based on the combination of explicit node masking and programmable ray operations. More complex ray tracing effects are enabled by providing for dynamic selection of nodes based on individual ray characteristics.
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公开(公告)号：US11704863B2
公开(公告)日：2023-07-18
申请号：US17716599
申请日：2022-04-08
Applicant: NVIDIA Corporation
Inventor： Samuli Laine , Tero Karras , Timo Aila , Robert Ohannessian , William Parsons Newhall, Jr. , Greg Muthler , Ian Kwong , Peter Nelson , John Burgess
CPC classification number: G06T15/06 , G06T15/005
Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to properly handle numerically challenging computations at or near edges and/or vertices of primitives and/or ensure that a single intersection is reported when a ray intersects a surface formed by primitives at or near edges and/or vertices of the primitives.
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公开(公告)号：US11675704B2
公开(公告)日：2023-06-13
申请号：US17483133
申请日：2021-09-23
Applicant: NVIDIA Corporation
Inventor： Greg Muthler , Timo Aila , Tero Karras , Samuli Laine , William Parsons Newhall, Jr. , Ronald Charles Babich, Jr. , John Burgess , Ignacio Llamas
IPC: G06F12/00 , G06F12/0875 , G06T15/06 , G06F16/901
CPC classification number: G06F12/0875 , G06F16/9027 , G06T15/06 , G06T2207/20021
Abstract: In a ray tracer, a cache for streaming workloads groups ray requests for coherent successive bounding volume hierarchy traversal operations by sending common data down an attached data path to all ray requests in the group at the same time or about the same time. Grouping the requests provides good performance with a smaller number of cache lines.
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