公开(公告)号：US20080224176A1

公开(公告)日：2008-09-18

申请号：US12048837

申请日：2008-03-14

申请人： Kazuyuki Nakanishi ,  Hidetoshi Nishimura ,  Tomoaki Ikegami

发明人： Kazuyuki Nakanishi ,  Hidetoshi Nishimura ,  Tomoaki Ikegami

IPC分类号： H01L27/10

CPC分类号： H01L27/0203 ,  H01L27/11807

摘要： A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C3, . . . ), each including gates G extended in the vertical direction, are aligned in the transverse direction to form a standard cell row. A plurality of the standard cell rows are located side by side in the vertical direction to form a standard cell group. Each of the standard cell rows has a terminal standard cell Ce at least one end of the standard cell row. The terminal standard cell Ce includes two or more supplementary gates, each of which is any of a dummy gate and a gate of an inactive transistor.

摘要翻译： 提供了一种半导体集成电路，其不需要增加OPC的校正时间，并且可靠地抑制由于光学邻近效应引起的栅极长度的不均匀性。 在垂直方向上延伸的包括栅极G的多个标准单元（C 1，C 2，C 3，...）在横向方向上排列以形成标准单元行。 多个标准单元行在垂直方向上并排设置以形成标准单元组。 每个标准单元行在标准单元行的至少一端具有端子标准单元Ce。 终端标准单元Ce包括两个或更多个辅助栅极，每个补充栅极是无源晶体管的伪栅极和栅极中的任一个。

公开(公告)号：US08592598B2

公开(公告)日：2013-11-26

申请号：US11662740

申请日：2005-09-13

申请人： Masayoshi Kaneko ,  Shigeo Yabuno ,  Kenji Iwaoka ,  Hidetoshi Nishimura

发明人： Masayoshi Kaneko ,  Shigeo Yabuno ,  Kenji Iwaoka ,  Hidetoshi Nishimura

IPC分类号： C07D401/12

CPC分类号： C07D401/12

摘要： The instant invention describes a method of producing a crystal of an imidazole compound or a salt thereof, which comprises suspending a solvate of the imidazole compound into a solution containing water, alcohol, and a basic substance.

摘要翻译： 本发明描述了制备咪唑化合物或其盐的晶体的方法，其包括将咪唑化合物的溶剂化物悬浮在含有水，醇和碱性物质的溶液中。

公开(公告)号：US20130286191A1

公开(公告)日：2013-10-31

申请号：US13997496

申请日：2011-11-02

申请人： Masaaki Ito ,  Hidetoshi Nishimura ,  Takahiro Jingu

发明人： Masaaki Ito ,  Hidetoshi Nishimura ,  Takahiro Jingu

IPC分类号： H04N7/18

CPC分类号： H04N7/18 ,  G01N21/47 ,  G01N21/9501 ,  G01N21/956 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a defect inspecting apparatus, the strength of a fatal defect signal decreases due to miniaturization. Thus, in order to assure a high SN ratio, it is necessary to reduce noises caused by scattered light from a wafer. Roughness of a pattern edge and surface roughness which serve as a scattered-light source are spread over the entire wafer. The present invention has discovered the fact that reduction of an illuminated area is a technique effective for decreasing noises. That is to say, the present invention has discovered the fact that creation of an illuminated area having a spot shape and reduction of the dimension of a spot beam are effective. A plurality of temporally and spatially divided spot beams are radiated to the wafer serving as a sample.

摘要翻译： 在缺陷检查装置中，致命缺陷信号的强度由于小型化而降低。 因此，为了确保高的SN比，需要减少由晶片散射的光产生的噪声。 用作散射光源的图案边缘和表面粗糙度的粗糙度分布在整个晶片上。 本发明已经发现，减少照明区域是有效降低噪声的技术。 也就是说，本发明已经发现了具有斑点形状的照明区域的创建和点光束的尺寸的减小的事实是有效的。 将多个时间上和空间上分开的光束照射到作为样品的晶片。

公开(公告)号：US08368225B2

公开(公告)日：2013-02-05

申请号：US13113644

申请日：2011-05-23

申请人： Tomoaki Ikegami ,  Hidetoshi Nishimura ,  Kazuyuki Nakanishi

发明人： Tomoaki Ikegami ,  Hidetoshi Nishimura ,  Kazuyuki Nakanishi

IPC分类号： H01L23/52 ,  H01L27/04

CPC分类号： H01L27/04 ,  H01L27/0207 ,  H01L27/11807

摘要： A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.

摘要翻译： 提供半导体集成电路的布局结构，可以防止在单元边界附近的金属互连的变窄和断开，而不增加OPC的数据量和处理时间。 单元格A和单元格B沿着单元边界彼此相邻。 相对于单元边界，金属互连的连接区域与单元边界不存在其他互连区域被放置为基本上是轴对称的，而面向单元边界的扩散区域的边相对于单元边界是不对称的。

公开(公告)号：US07923755B2

公开(公告)日：2011-04-12

申请号：US12857138

申请日：2010-08-16

申请人： Emi Mizushino ,  Hidetoshi Nishimura ,  Junichi Yano

发明人： Emi Mizushino ,  Hidetoshi Nishimura ,  Junichi Yano

IPC分类号： H01L27/118 ,  H03K19/00

CPC分类号： H01L27/11807 ,  H01L27/0203

摘要： In the present invention, a decoupling capacitance circuit, a first output terminal and a second output terminal are provided. The decoupling capacitance circuit comprises a TDDB control circuit consisting of a first Tr and a second Tr, and a third Tr. Conductivity types of the first and second Trs are different from each other. A source of the first Tr is connected to a first power supply wiring, and a drain of the first Tr is connected to a gate of the second Tr. A source of the second Tr is connected to a second power supply wiring, and a drain of the second Tr is connected to a gate of the first Tr. The third and first Trs have the same conductivity type. A source and a drain of the third Tr are connected to the first power supply wiring, and a gate of the third Tr is connected to the drain of the second Tr. The first output terminal is connected to the drain of the first Tr, and the second output terminal is connected to the drain of the second Tr.

摘要翻译： 在本发明中，提供了去耦电容电路，第一输出端子和第二输出端子。 去耦电容电路包括由第一Tr和第二Tr组成的TDDB控制电路和第三Tr。 第一和第二Tr的电导率类型彼此不同。 第一Tr的源极连接到第一电源布线，第一Tr的漏极连接到第二Tr的栅极。 第二Tr的源极连接到第二电源布线，第二Tr的漏极连接到第一Tr的栅极。 第三和第一Trs具有相同的导电类型。 第三Tr的源极和漏极连接到第一电源布线，第三Tr的栅极连接到第二Tr的漏极。 第一输出端子连接到第一Tr的漏极，第二输出端子连接到第二Tr的漏极。

公开(公告)号：US07800140B2

公开(公告)日：2010-09-21

申请号：US12048837

申请日：2008-03-14

申请人： Kazuyuki Nakanishi ,  Hidetoshi Nishimura ,  Tomoaki Ikegami

发明人： Kazuyuki Nakanishi ,  Hidetoshi Nishimura ,  Tomoaki Ikegami

IPC分类号： H01L27/10

CPC分类号： H01L27/0203 ,  H01L27/11807

摘要： A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C3, . . . ), each including gates G extended in the vertical direction, are aligned in the transverse direction to form a standard cell row. A plurality of the standard cell rows are located side by side in the vertical direction to form a standard cell group. Each of the standard cell rows has a terminal standard cell Ce at least one end of the standard cell row. The terminal standard cell Ce includes two or more supplementary gates, each of which is any of a dummy gate and a gate of an inactive transistor.

摘要翻译： 提供了一种半导体集成电路，其不需要增加OPC的校正时间，并且可靠地抑制由于光学邻近效应引起的栅极长度的不均匀性。 多个标准单元（C1，C2，C3 ...）各自包括在垂直方向上延伸的栅极G，在横向方向上排列以形成标准单元行。 多个标准单元行在垂直方向上并排设置以形成标准单元组。 每个标准单元行在标准单元行的至少一端具有端子标准单元Ce。 终端标准单元Ce包括两个或更多个辅助栅极，每个补充栅极是无源晶体管的伪栅极和栅极中的任一个。

公开(公告)号：US20100187699A1

公开(公告)日：2010-07-29

申请号：US12524998

申请日：2009-02-24

申请人： Hidetoshi Nishimura ,  Hiroyuki Shimbo ,  Tetsurou Toubou ,  Hiroki Taniguchi ,  Hisako Yoneda

发明人： Hidetoshi Nishimura ,  Hiroyuki Shimbo ,  Tetsurou Toubou ,  Hiroki Taniguchi ,  Hisako Yoneda

IPC分类号： H01L23/49

CPC分类号： H01L27/0207 ,  H01L23/522 ,  H01L23/5286 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a layout structure of a semiconductor integrated circuit capable of preventing the thinning of a metal wiring line close to a cell boundary and wire breakage therein without involving increases in the amount of data for OPC correction and OPC process time. In a region interposed between a power supply line and a ground line each placed to extend in a first direction, first and second cells each having a transistor and an intra-cell line each for implementing a circuit function are placed to be adjacent to each other in the first direction. In a boundary portion between the first and second cells, a metal wiring line extending in a second direction orthogonal to the first direction is placed so as not to short-circuit the power supply line and the ground line.

摘要翻译： 提供了一种半导体集成电路的布局结构，其能够防止金属布线在细胞边界附近的细化和线断裂，而不涉及用于OPC校正和OPC处理时间的数据量的增加。 在放置在第一方向上延伸的电源线和接地线之间的区域中，分别具有用于实现电路功能的晶体管和单元间线路的第一和第二单元彼此相邻 在第一个方向。 在第一和第二单元之间的边界部分中，放置沿与第一方向正交的第二方向延伸的金属布线，以便不使电源线和接地线短路。

公开(公告)号：US20060071319A1

公开(公告)日：2006-04-06

申请号：US11229503

申请日：2005-09-20

申请人： Hidetoshi Nishimura

发明人： Hidetoshi Nishimura

IPC分类号： H01L21/4763 ,  H01L23/52

CPC分类号： H01L21/76838 ,  H01L27/11807

摘要： In a semiconductor integrated circuit including a plurality of cells, a supplementary power-supply wire is disposed between a lattice-shaped upper power-supply wire and a lower cell power-supply wire for cases in which power is supplied from the upper power-supply wire to the lower cell power-supply wire. The supplementary power-supply wire and the lower cell power-supply wire are connected by two vias. The supplementary power-supply wire and the upper power-supply wire are connected by a single via. Current from the supplementary power-supply wire is divided by the two vias and then supplied to the lower cell power-supply wire. Therefore, when power is supplied from the upper power-supply wire to the lower cell power-supply wire, current concentration at the connection points of the lower cell power-supply wire to the vias is decreased, thereby reducing wire breaks caused by EM (electro migration).

摘要翻译： 在包括多个单电池的半导体集成电路中，在格状的上电源线和下电池电源线之间配置辅助电源线，用于从上电源 连接到下电池电源线。 辅助电源线和下电池电源线通过两个通孔连接。 辅助电源线和上电源线通过单个通孔连接。 辅助电源线的电流由两个通孔分开，然后提供给下电池电源线。 因此，当从上电源线向下电池电源线供电时，下电池电源线到通孔的连接点处的电流集中减少，从而减少EM产生的断线 电迁移）。

公开(公告)号：US06791391B2

公开(公告)日：2004-09-14

申请号：US10193442

申请日：2002-07-10

申请人： Hidetoshi Nishimura ,  Masahiro Gion ,  Heiji Ikoma ,  Naoki Nojiri

发明人： Hidetoshi Nishimura ,  Masahiro Gion ,  Heiji Ikoma ,  Naoki Nojiri

IPC分类号： H03L500

CPC分类号： H03K3/012 ,  H03K3/356113

摘要： In a CMOS level shifting circuit including N-channel transistors that have sources to which a digital signal is supplied, a bias voltage Vref is supplied to gates of the N-channel transistors, and the bias voltage Vref is set to be higher than a high level voltage of the digital signal and lower than a value obtained by adding a threshold voltage of the N-channel transistors to the high level voltage of the digital signal. Thus, a level shifting circuit is provided that is capable of outputting a signal having subjected to stable level conversion, even when a voltage level of a low voltage signal is lowered.

摘要翻译： 在包括具有提供数字信号的源的N沟道晶体管的CMOS电平移动电路中，偏置电压Vref被提供给N沟道晶体管的栅极，偏置电压Vref被设置为高于高电平 数字信号的电平电压低于通过将N沟道晶体管的阈值电压加到数字信号的高电平电平而获得的值。 因此，即使当低电压信号的电压电平降低时，也提供能够输出经过稳定电平转换的信号的电平移位电路。