公开(公告)号：US20080203439A1

公开(公告)日：2008-08-28

申请号：US12081730

申请日：2008-04-21

申请人： Yoshihiro Nonaka

发明人： Yoshihiro Nonaka

IPC分类号： H01L27/12

CPC分类号： H01L27/1214 ,  G06F17/5068 ,  G06F17/5077 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： A layout for placing a circuit having a plurality of transistors in a small-width region. A search section inputs data on a circuit and searches for a set of routes formed so that passage through a transistor occurs only one time and so that the combination of routes covers the entire circuit network. An extraction section extracts a set of routes having the smallest number of routes. A width determination section determines the layout width from source and drain electrodes, the region between the source and drain electrodes, the region between adjacent pairs of the transistors not combined into a common electrode, the number of transistors, and the smallest number of routes. A layout determination section forms a layout in which the source, drain and gate electrodes of the transistor included in the circuit are placed in a small-width region.

摘要翻译： 用于将具有多个晶体管的电路放置在小宽度区域中的布局。 搜索部分输入电路上的数据，并搜索形成的一组路由，使得通过晶体管只发生一次，从而路由的组合覆盖整个电路网络。 提取部分提取具有最小路由数的一组路由。 宽度确定部分确定来自源极和漏极的布局宽度，源极和漏极之间的区域，未组合成公共电极的晶体管的相邻对之间的区域，晶体管的数量和最小数量的路径。 布局确定部分形成包括在电路中的晶体管的源极，漏极和栅电极放置在小宽度区域中的布局。

公开(公告)号：US07294891B2

公开(公告)日：2007-11-13

申请号：US10648256

申请日：2003-08-27

申请人： Yoshihiro Nonaka

发明人： Yoshihiro Nonaka

IPC分类号： H01L29/76

CPC分类号： H01L27/1214 ,  G06F17/5068 ,  G06F17/5077 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： A layout capable of placing a circuit constituted by a plurality of transistors in a small-with region is automatically formed. A search section inputs data on a circuit and makes a search for a set of routes formed so that passage through any one of the transistors occurs only one time and so that the combination of routes in one set can cover the entire circuit network. An extraction section extracts a set of routes having the smallest number of routes in sets of route found by searching. A width determination section determines the layout width from the widths of source and drain electrodes of each transistor, the width of the region between the source and drain electrodes, the width of the region between some of the adjacent pairs of the transistors not combined into a common electrode, the number of transistors, and the smallest number of routes. A layout determination section forms information on a layout in which all the source, drain and gate electrodes of the transistor included in the circuit are placed in a small-width region having the determined width.

摘要翻译： 自动形成能够将由多个晶体管构成的电路放置在小区域中的布局。 搜索部分输入电路上的数据并搜索形成的路由集合，使得通过任何一个晶体管只有一次，并且使得一组中的路由的组合可以覆盖整个电路网络。 提取部分提取通过搜索找到的路由集合中具有最小路由数的一组路由。 宽度确定部分从每个晶体管的源极和漏极的宽度，源极和漏极之间的区域的宽度，未组合成一个晶体管的一些相邻晶体管之间的区域的宽度确定布局宽度 公共电极，晶体管数量和最小路线数量。 布局确定部分形成关于布局的信息，其中包括在电路中的晶体管的所有源极，漏极和栅极电极放置在具有确定的宽度的小宽度区域中。

公开(公告)号：US20050179039A1

公开(公告)日：2005-08-18

申请号：US11055781

申请日：2005-02-11

申请人： Yoshihiro Nonaka

发明人： Yoshihiro Nonaka

IPC分类号： G02F1/1343 ,  G02F1/133 ,  G02F1/1345 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/00 ,  G09G3/20 ,  G09G3/30 ,  G09G3/36 ,  H01L27/02 ,  H01L27/12 ,  H01L29/04 ,  H02M3/00

CPC分类号： G09G3/3696 ,  G02F1/13454 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2330/02 ,  H01L27/0203 ,  H01L27/12

摘要： The present invention relates to a semiconductor device in which a power supply circuit is disposed on an array substrate, which achieves reduction of the size by suppressing an increase of the area occupied by the power supply wiring. The feature of the present invention is that a power supply circuit is disposed adjacent to a supply voltage input terminal and a signal line driving circuit. An extremely large amount of electric current is flown in a power supply wiring between the power supply circuit and the supply voltage input terminal and a power supply wiring between the power supply circuit and the signal line driving circuit. Thus, by disposing the power supply circuit adjacent to the supply voltage input terminal and the signal line driving circuit, the power supply wirings therebetween can be shortened. Accordingly, the wiring resistance proportional to the product of the length and the width becomes small so that the thinned power supply wiring can be tolerated. As a result, the power supply wirings can be shortened and thinned so that the wiring area can be decreased.

摘要翻译： 本发明涉及一种半导体器件，其中电源电路设置在阵列基板上，通过抑制电源布线占用面积的增加来实现尺寸的减小。 本发明的特征在于电源电路与电源电压输入端子和信号线驱动电路相邻配置。 在电源电路和电源电压输入端子之间的电源布线中以及电源电路和信号线驱动电路之间的电源布线中流过极大量的电流。 因此，通过将电源电路配置在与电源电压输入端子和信号线驱动电路相邻的位置，能够缩短电源配线。 因此，与长度和宽度的乘积成比例的布线电阻变小，从而可以容忍变薄的电源布线。 结果，电源布线可以被缩短和变薄，使得布线面积可以减小。

公开(公告)号：US20100289994A1

公开(公告)日：2010-11-18

申请号：US12778753

申请日：2010-05-12

申请人： Yoshihiro Nonaka

发明人： Yoshihiro Nonaka

IPC分类号： G02F1/1335

CPC分类号： G02F1/133514 ,  G02F1/1368 ,  G02F2001/133388 ,  G02F2201/52 ,  G02F2201/56 ,  G09G3/20 ,  G09G2300/0426

摘要： A color image display device is provided which is capable of displaying an image with no differences in color balance between end portions and inner portions of anon-rectangle image display region. The color image display device includes an end portion unit pixel formed in an edge portion of a display region in which a color image is displayed and including end portion sub-pixels which correspond to a plurality of kinds of primary colors respectively in a one-to-one relationship and an inner unit pixel formed in an inside of the display region with respect to the end portion unit pixels and including inner sub-pixels which correspond to the plurality of kinds of primary colors respectively in a one-to-one relationship. With such a configuration, a relative area proportion of the end portion sub-pixels that correspond to the primary colors respectively in a one-to-one relationship is set equal to that of the inner sub-pixels that correspond to the primary colors respectively in a one-to-one relationship. The plurality of kinds of the end portion sub-pixels is arrayed in accordance with a position or a shape on an outer edge of the display region, an array direction of the plurality of kinds of the end portion sub-pixels and an array direction of the plurality of kinds of the inner sub-pixels configured to intersect each other.

摘要翻译： 本发明提供一种能够显示出在非整形图像显示区域的端部和内部之间的颜色平衡没有差别的图像的彩色图像显示装置。 彩色图像显示装置包括形成在其中显示彩色图像的显示区域的边缘部分中的端部单元像素，并且包括分别对应于多种基色的端部子像素 - 一个关系和内部单元像素，其相对于端部单元像素形成在显示区域的内部，并且分别包括与一对一关系中的多种基色对应的内部子像素。 通过这样的结构，将分别对应于原色的端部子像素的一对一关系的相对面积比例设定为与分别对应于原色的内部子像素的相对面积比例相等 一对一的关系。 根据显示区域的外边缘上的位置或形状，多个端部子像素的排列方向和多个端部子像素的排列方向排列多个端部子像素 所述多个内部子像素被配置为彼此相交。

公开(公告)号：US07376923B2

公开(公告)日：2008-05-20

申请号：US11517258

申请日：2006-09-08

申请人： Yoshihiro Nonaka

发明人： Yoshihiro Nonaka

IPC分类号： G06F17/50

CPC分类号： H01L27/1214 ,  G06F17/5068 ,  G06F17/5077 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： A layout capable of placing a circuit constituted by a plurality of transistors in a small-with region is automatically formed. A search section inputs data on a circuit and makes a search for a set of routes formed so that passage through any one of the transistors occurs only one time and so that the combination of routes in one set can cover the entire circuit network. An extraction section extracts a set of routes having the smallest number of routes in sets of route found by searching. A width determination section determines the layout width from the widths of source and drain electrodes of each transistor, the width of the region between the source and drain electrodes, the width of the region between some of the adjacent pairs of the transistors not combined into a common electrode, the number of transistors, and the smallest number of routes. A layout determination section forms information on a layout in which all the source, drain and gate electrodes of the transistor included in the circuit are placed in a small-width region having the determined width.

摘要翻译： 自动形成能够将由多个晶体管构成的电路放置在小区域中的布局。 搜索部分输入电路上的数据并搜索形成的路由集合，使得通过任何一个晶体管只有一次，并且使得一组中的路由的组合可以覆盖整个电路网络。 提取部分提取通过搜索找到的路由集合中具有最小路由数的一组路由。 宽度确定部分从每个晶体管的源极和漏极的宽度，源极和漏极之间的区域的宽度，未组合成一个晶体管的一些相邻晶体管之间的区域的宽度确定布局宽度 公共电极，晶体管数量和最小路线数量。 布局确定部分形成关于布局的信息，其中包括在电路中的晶体管的所有源极，漏极和栅极电极放置在具有确定的宽度的小宽度区域中。

公开(公告)号：US20060109225A1

公开(公告)日：2006-05-25

申请号：US11229380

申请日：2005-09-19

申请人： Hiroshi Haga ,  Tomohiko Otose ,  Hideki Asada ,  Yoshihiro Nonaka ,  Takahiro Korenari ,  Kenichi Takatori

发明人： Hiroshi Haga ,  Tomohiko Otose ,  Hideki Asada ,  Yoshihiro Nonaka ,  Takahiro Korenari ,  Kenichi Takatori

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/08 ,  G09G2310/027 ,  G09G2310/0289 ,  G09G2310/0297

摘要： A device excellent in electrical characteristics is provided by suppressing an operation failure owing to a hysteresis effect that occurs in a circuit using MOS transistors having floating bodies. Moreover, sensitivity of a sense amplifier circuit and a latch circuit including these MOS transistors as components is improved. A signal required in a circuit other than a first circuit is outputted by using electrical characteristics of MOS transistors in a first period (effective period), and in a second period (idle period) excluding the first period, between the gate and source of MOS transistors, a step waveform voltage not less than threshold voltages of these MOS transistors is given.

摘要翻译： 通过抑制由于在使用具有浮体的MOS晶体管的电路中发生的滞后效应而导致的操作故障，提供了电特性优异的装置。 此外，提高了包括这些MOS晶体管的读出放大器电路和锁存电路的灵敏度。 在第一周期（有效期）内，在MOS晶体管的栅极与源极之间的第二周期（第一周期内的空闲周期）中，通过使用MOS晶体管的电气特性，输出除第一电路以外的电路所需的信号 给出了不低于这些MOS晶体管的阈值电压的阶跃波形电压。