公开(公告)号：US08681084B2

公开(公告)日：2014-03-25

申请号：US11229380

申请日：2005-09-19

申请人： Hiroshi Haga ,  Tomohiko Otose ,  Hideki Asada ,  Yoshihiro Nonaka ,  Takahiro Korenari ,  Kenichi Takatori

发明人： Hiroshi Haga ,  Tomohiko Otose ,  Hideki Asada ,  Yoshihiro Nonaka ,  Takahiro Korenari ,  Kenichi Takatori

IPC分类号： G09G3/36 ,  G09G5/00 ,  G06F3/038

CPC分类号： G09G3/3648 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/08 ,  G09G2310/027 ,  G09G2310/0289 ,  G09G2310/0297

摘要： A device excellent in electrical characteristics is provided by suppressing an operation failure owing to a hysteresis effect that occurs in a circuit using MOS transistors having floating bodies. Moreover, sensitivity of a sense amplifier circuit and a latch circuit including these MOS transistors as components is improved. A signal required in a circuit other than a first circuit is outputted by using electrical characteristics of MOS transistors in a first period (effective period), and in a second period (idle period) excluding the first period, between the gate and source of MOS transistors, a step waveform voltage not less than threshold voltages of these MOS transistors is given.

摘要翻译： 通过抑制由于在使用具有浮体的MOS晶体管的电路中发生的滞后效应而导致的操作故障，提供了电特性优异的装置。 此外，提高了包括这些MOS晶体管的读出放大器电路和锁存电路的灵敏度。 在第一周期（有效期）内，在MOS晶体管的栅极与源极之间的第二周期（第一周期内的空闲周期）中，通过使用MOS晶体管的电气特性，输出除第一电路以外的电路所需的信号 给出了不低于这些MOS晶体管的阈值电压的阶跃波形电压。

公开(公告)号：US08451414B2

公开(公告)日：2013-05-28

申请号：US12778753

申请日：2010-05-12

申请人： Yoshihiro Nonaka

发明人： Yoshihiro Nonaka

IPC分类号： G02F1/1343

CPC分类号： G02F1/133514 ,  G02F1/1368 ,  G02F2001/133388 ,  G02F2201/52 ,  G02F2201/56 ,  G09G3/20 ,  G09G2300/0426

摘要： A color image display device is provided which is capable of displaying an image with no differences in color balance between end portions and inner portions of anon-rectangle image display region. The color image display device includes an end portion unit pixel formed in an edge portion of a display region in which a color image is displayed and including end portion sub-pixels which correspond to a plurality of kinds of primary colors respectively in a one-to-one relationship and an inner unit pixel formed in an inside of the display region with respect to the end portion unit pixels and including inner sub-pixels which correspond to the plurality of kinds of primary colors respectively in a one-to-one relationship. With such a configuration, a relative area proportion of the end portion sub-pixels that correspond to the primary colors respectively in a one-to-one relationship is set equal to that of the inner sub-pixels that correspond to the primary colors respectively in a one-to-one relationship. The plurality of kinds of the end portion sub-pixels is arrayed in accordance with a position or a shape on an outer edge of the display region, an array direction of the plurality of kinds of the end portion sub-pixels and an array direction of the plurality of kinds of the inner sub-pixels configured to intersect each other.

摘要翻译： 本发明提供一种能够显示出在非整形图像显示区域的端部和内部之间的颜色平衡没有差别的图像的彩色图像显示装置。 彩色图像显示装置包括形成在其中显示彩色图像的显示区域的边缘部分中的端部单元像素，并且包括分别对应于多种基色的端部子像素 - 一个关系和内部单元像素，其相对于端部单元像素形成在显示区域的内部，并且分别包括与一对一关系中的多种基色对应的内部子像素。 通过这样的结构，将分别对应于原色的端部子像素的一对一关系的相对面积比例设定为与分别对应于原色的内部子像素的相对面积比例相等 一对一的关系。 根据显示区域的外边缘上的位置或形状，多个端部子像素的排列方向和多个端部子像素的排列方向排列多个端部子像素 所述多个内部子像素被配置为彼此相交。

公开(公告)号：US08264476B2

公开(公告)日：2012-09-11

申请号：US11055781

申请日：2005-02-11

申请人： Yoshihiro Nonaka

发明人： Yoshihiro Nonaka

IPC分类号： G06F3/041

CPC分类号： G09G3/3696 ,  G02F1/13454 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2330/02 ,  H01L27/0203 ,  H01L27/12

摘要： The present invention relates to a semiconductor device in which a power supply circuit is disposed on an array substrate, which achieves reduction of the size by suppressing an increase of the area occupied by the power supply wiring. The feature of the present invention is that a power supply circuit is disposed adjacent to a supply voltage input terminal and a signal line driving circuit. An extremely large amount of electric current is flown in a power supply wiring between the power supply circuit and the supply voltage input terminal and a power supply wiring between the power supply circuit and the signal line driving circuit. Thus, by disposing the power supply circuit adjacent to the supply voltage input terminal and the signal line driving circuit, the power supply wirings therebetween can be shortened. Accordingly, the wiring resistance proportional to the product of the length and the width becomes small so that the thinned power supply wiring can be tolerated. As a result, the power supply wirings can be shortened and thinned so that the wiring area can be decreased.

摘要翻译： 本发明涉及一种半导体器件，其中电源电路设置在阵列基板上，通过抑制电源布线占用面积的增加来实现尺寸的减小。 本发明的特征在于电源电路与电源电压输入端子和信号线驱动电路相邻配置。 在电源电路和电源电压输入端子之间的电源布线中以及电源电路和信号线驱动电路之间的电源布线中流过极大量的电流。 因此，通过将电源电路配置在与电源电压输入端子和信号线驱动电路相邻的位置，能够缩短电源配线。 因此，与长度和宽度的乘积成比例的布线电阻变小，从而可以容忍变薄的电源布线。 结果，电源布线可以被缩短和变薄，使得布线面积可以减小。

公开(公告)号：US07564297B2

公开(公告)日：2009-07-21

申请号：US11842651

申请日：2007-08-21

申请人： Yoshihiro Nonaka

发明人： Yoshihiro Nonaka

IPC分类号： G05F1/10

CPC分类号： H02M3/07

摘要： A power supply circuit is provided which is capable of preventing a drop in an output voltage of the power supply circuit used as a DC/DC converter made up of single and conductive type (n-type or p-type) MOS transistors and of improving efficiency. Since a control voltage having an amplitude [2×VDD] is applied from a level shift circuit to a charge-pump circuit, even when potentials at nodes becomes a level [2×VDD], pMOS transistors are kept in an OFF state, thereby preventing leakage of currents from pMOS transistors. This avoids a drop in an DC output voltage. As inputs to the level shift circuits, potentials at nodes of the charge-pump circuit are used and, therefore, even if potentials at nodes of the level shift circuits are high, pMOS transistors are kept in an OFF state.

摘要翻译： 提供一种电源电路，其能够防止用作由单导电型（n型或p型）MOS晶体管构成的DC / DC转换器的电源电路的输出电压下降，并且改善 效率。 由于具有振幅[2xVDD]的控制电压从电平移位电路施加到电荷泵电路，所以即使在节点处的电位变为电平[2xVDD]时，pMOS晶体管保持在截止状态，从而防止电流泄漏 来自pMOS晶体管。 这避免了直流输出电压的下降。 作为电平移位电路的输入，使用电荷泵电路的节点处的电位，因此即使电平移位电路的节点的电位高，pMOS晶体管也保持在截止状态。

公开(公告)号：US20060114608A1

公开(公告)日：2006-06-01

申请号：US11333897

申请日：2006-01-18

申请人： Shinsaku Saitho ,  Haruo Urai ,  Nobuyuki Ishiwata ,  Kiyotaka Shimabayashi ,  Yoshihiro Nonaka ,  Tamaki Toba

发明人： Shinsaku Saitho ,  Haruo Urai ,  Nobuyuki Ishiwata ,  Kiyotaka Shimabayashi ,  Yoshihiro Nonaka ,  Tamaki Toba

IPC分类号： G11B5/147

CPC分类号： G11B5/3967 ,  G11B5/3116 ,  G11B5/313

摘要： To accurately decrease the gap depth between an upper pole layer and a lower pole layer and the front-end portion width of the upper pole layer. A thin-film magnetic head of the present invention is constituted by forming a lower shielding layer, a read gap layer holding an MR magnetosensitive element, a common pole layer, and a write gap layer in order on an insulating substrate, forming a first flattening layer, a coil pattern layer, and a second flattening layer laminated in order on the write gap layer excluding the vicinity of an ABS plane, and forming an upper pole layer on the write gap layer and the second flattening layer nearby an ABS plane. Moreover, a concave portion is formed on the common pole layer at a position separated from the ABS plane, the concave portion is filled with a nonmagnetic body, and the gap depth between the upper pole layer and the common pole layer is determined by the concave portion.

公开(公告)号：US07054107B2

公开(公告)日：2006-05-30

申请号：US10375239

申请日：2003-02-27

申请人： Shinsaku Saitho ,  Haruo Urai ,  Nobuyuki Ishiwata ,  Kiyotaka Shimabayashi ,  Yoshihiro Nonaka ,  Tamaki Toba

发明人： Shinsaku Saitho ,  Haruo Urai ,  Nobuyuki Ishiwata ,  Kiyotaka Shimabayashi ,  Yoshihiro Nonaka ,  Tamaki Toba

IPC分类号： G11B5/147

CPC分类号： G11B5/3967 ,  G11B5/3116 ,  G11B5/313

摘要： To accurately decrease the gap depth between an upper pole layer and a lower pole layer and the front-end portion width of the upper pole layer.A thin-film magnetic head of the present invention is constituted by forming a lower shielding layer, a read gap layer holding an MR magnetosensitive element, a common pole layer, and a write gap layer in order on an insulating substrate, forming a first flattening layer, a coil pattern layer, and a second flattening layer laminated in order on the write gap layer excluding the vicinity of an ABS plane, and forming an upper pole layer on the write gap layer and the second flattening layer nearby an ABS plane. Moreover, a concave portion is formed on the common pole layer at a position separated from the ABS plane, the concave portion is filled with a nonmagnetic body, and the gap depth between the upper pole layer and the common pole layer is determined by the concave portion.

摘要翻译： 为了精确地减小上极层和下极层之间的间隙深度和上极层的前端部宽度。 本发明的薄膜磁头通过在绝缘基板上依次形成下屏蔽层，保持MR磁敏元件，公共极层和写间隙层的读取间隙层，形成第一扁平化 层，线圈图案层和在除了ABS平面附近的写入间隙层上顺序层叠的第二平坦化层，并且在ABS平面附近的写间隙层和第二平坦化层上形成上极层。 此外，在与ABS平面分离的位置处，在公共极层上形成凹部，凹部填充有非磁性体，上极层和公共极层之间的间隙深度由凹部 一部分。

公开(公告)号：US20060103429A1

公开(公告)日：2006-05-18

申请号：US11274165

申请日：2005-11-16

申请人： Yoshihiro Nonaka

发明人： Yoshihiro Nonaka

IPC分类号： H03K19/094 ,  H03K19/0175

CPC分类号： G09G3/3677 ,  H03K17/063 ,  H03K19/01735

摘要： A bootstrap circuit includes an output transistor, a bootstrap capacitor provided between the gate and source of the output transistor, a power source, and a circuit that performs ON/OFF control of a supply from the power source to the gate electrode of the transistor. An initial voltage before a bootstrap effect can be set to the potential of the power source, which is independent of the threshold voltage of the transistor. Therefore, the source output of the transistor rising or dropping due to the bootstrap effect is not affected by variations that depend on the threshold voltage of the transistor.

公开(公告)号：US07023659B2

公开(公告)日：2006-04-04

申请号：US10815069

申请日：2004-03-31

申请人： Hiroaki Honjo ,  Tsutomu Ishi ,  Mikiko Saito ,  Shinsaku Saito ,  Tamaki Toba ,  Yoshihiro Nonaka ,  Kazuhiko Hayashi ,  Nobuyuki Ishiwata

发明人： Hiroaki Honjo ,  Tsutomu Ishi ,  Mikiko Saito ,  Shinsaku Saito ,  Tamaki Toba ,  Yoshihiro Nonaka ,  Kazuhiko Hayashi ,  Nobuyuki Ishiwata

IPC分类号： G11B5/147

CPC分类号： B82Y25/00 ,  B82Y10/00 ,  G11B5/00 ,  G11B5/3103 ,  G11B5/3109 ,  G11B5/3116 ,  G11B5/3133 ,  G11B5/314 ,  G11B5/3143 ,  G11B5/3163 ,  G11B5/3967 ,  G11B5/40 ,  G11B2005/3996 ,  Y10T29/49044

摘要： By inserting a first antistripping layer comprising a first non-magnetic layer 22 and a first conductive layer 23 between a first magnetic layer 16 and a magnetic separation layer 13, adhesion between the first conductive layer 23 and the magnetic separation layer 13 is improved to prevent the first magnetic layer 16 from stripping. In addition, by inserting a second antistripping layer comprising a second non-magnetic layer 24 and a second conductive layer 25 between a second magnetic layer 21 and a magnetic gap layer 17, adhesion between the second conductive layer 24 and the magnetic gap layer 17 is improved to prevent the second magnetic layer 25 from stripping.

公开(公告)号：US07005912B2

公开(公告)日：2006-02-28

申请号：US10684441

申请日：2003-10-15

申请人： Yoshihiro Nonaka

发明人： Yoshihiro Nonaka

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H02M3/073 ,  H02M2001/009 ,  H02M2003/071 ,  H02M2003/076

摘要： In a step-up apparatus, a first level shift circuit receives a first clock signal to generate two phase-opposite second clock signals, and a second level shift circuit receives the first clock signal to generate two phase-opposite third clock signals. A charge pump circuit steps up a power supply voltage at a power supply voltage terminal using the second clock signals to generate a positive voltage, and a polarity inverting circuit inverts the positive voltage using the third clock signals to generate a negative voltage whose absolute value is the same as the positive voltage. A high level of the second clock signals is not higher than the positive voltage, and a low level of the second clock signals is not lower than a voltage at a ground terminal. A high level of the third clock signals is not higher than the power supply voltage, and a low level of the third clock signals is not lower than the negative voltage.

摘要翻译： 在升压装置中，第一电平移位电路接收第一时钟信号以产生两个相对第二时钟信号，第二电平移位电路接收第一时钟信号以产生两个相反的第三时钟信号。 电荷泵电路使用第二时钟信号来升高电源电压端子处的电源电压，以产生正电压，并且极性反转电路使用第三时钟信号来反转正电压，以产生绝对值为 与正电压相同。 高电平的第二时钟信号不高于正电压，第二时钟信号的低电平不低于接地端子处的电压。 高电平的第三时钟信号不高于电源电压，并且第三时钟信号的低电平不低于负电压。

公开(公告)号：US20110050317A1

公开(公告)日：2011-03-03

申请号：US12873719

申请日：2010-09-01

申请人： Yoshihiro NONAKA

发明人： Yoshihiro NONAKA

IPC分类号： H03L5/00 ,  H03K17/56

CPC分类号： H03K17/04206

摘要： A bootstrap circuit comprises: a first transistor connecting a first power supply with an output node; and a second transistor applying a first input signal to a gate node of the first transistor and having a conductivity type identical to that of the first transistor. A second input signal obtained by inverting a level of the first input signal, delaying the inverted signal, and adding a direct current bias to the delayed signal is inputted to a gate node of the second transistor.

摘要翻译： 自举电路包括：将第一电源与输出节点连接的第一晶体管; 以及将第一输入信号施加到第一晶体管的栅极节点并具有与第一晶体管的导通类型相同的导电类型的第二晶体管。 通过将第一输入信号的电平反相，延迟反相信号和将延迟信号的直流偏置相加而获得的第二输入信号被输入到第二晶体管的栅极节点。