公开(公告)号：US20050210350A1

公开(公告)日：2005-09-22

申请号：US10914306

申请日：2004-08-09

Applicant: Pascal Urard

Inventor： Pascal Urard

IPC: H03H17/02 ,  H03H17/06 ,  G01R31/28 ,  G06F11/00

CPC classification number: H03H17/0294 ,  H03H17/0621

Abstract: A sampling rate converter includes a chain of identical cells connected in series. An input of a first cell of the chain receives input digital sampling values according to an input frequency. An output of the first cell then delivers output digital sampling values according to an output frequency. The input and output digital sampling values correspond to identical respective reconstruction curves, and the output frequency may be greater than or less than the input frequency. Each cell includes a storage element, two multipliers and two adders.

Abstract translation: 采样率转换器包括串联连接的相同单元的链。 链的第一单元的输入根据输入频率接收输入数字采样值。 然后，第一单元的输出根据输出频率输出输出数字采样值。 输入和输出数字采样值对应于相同的相应重建曲线，并且输出频率可以大于或小于输入频率。 每个单元包括存储元件，两个乘法器和两个加法器。

公开(公告)号：US08327033B2

公开(公告)日：2012-12-04

申请号：US12150599

申请日：2008-04-29

Applicant: Cyrille Chavet ,  Pascal Urard ,  Philippe Coussy ,  Eric Martin

Inventor： Cyrille Chavet ,  Pascal Urard ,  Philippe Coussy ,  Eric Martin

IPC: G06F3/00 ,  G06F13/00

CPC classification number: H03M13/2775 ,  H03M13/2957 ,  H04L1/0071

Abstract: A data interleaving device is provided that includes an input, an output, and a data interleaver coupled to the input and the output. The input receives data originating from a plurality of processing blocks. The output transfers interleaved data to the plurality of processing blocks. The data interleaver includes a controller, at least one interconnection module, and a plurality of memories. The controller prepares a data-to-memory assignment data structure. The at least one interconnection module switches data in parallel according to the data-to-memory assignment data structure and acts identically on all data switched simultaneously in parallel. The plurality of memories store the switched data. The data interleaver interleaves data received from the input and provides the interleaved data at the output.

Abstract translation: 提供了一种包括耦合到输入和输出的输入，输出和数据交织器的数据交织设备。 输入接收来自多个处理块的数据。 输出将交错数据传送到多个处理块。 数据交织器包括控制器，至少一个互连模块和多个存储器。 控制器准备数据到内存分配数据结构。 至少一个互连模块根据数据到存储器分配数据结构并行地切换数据，并且对并行地同时切换的所有数据执行相同的操作。 多个存储器存储切换的数据。 数据交织器交织从输入接收的数据，并在输出端提供交错数据。

公开(公告)号：US08046658B2

公开(公告)日：2011-10-25

申请号：US11834198

申请日：2007-08-06

Applicant: Vincent Heinrich ,  Pascal Urard

Inventor： Vincent Heinrich ,  Pascal Urard

IPC: H03M13/00

CPC classification number: H03M13/1165 ,  H03M13/1105 ,  H03M13/6505 ,  H03M13/6508 ,  H03M13/6566

Abstract: A method is for decoding a succession of blocks of data encoded with an LDPC code. The method includes storing the blocks temporarily and successively in an input memory before decoding the blocks successively in an iterative manner, the input memory having a memory size for storage of at least two blocks, and defining a current indication representative of a threshold number of iterations for decoding a current block. The method includes decoding the current block until a decoding criterion is satisfied or so long as a number of iterations performed for decoding the current block has not reached the current indication while at least one of a first subsequent block and a part of a second subsequent block are stored in the input memory, and updating the current indication for decoding the first subsequent block as a function of the number of iterations performed for decoding the current block.

Abstract translation: 一种用于解码用LDPC码编码的数据块序列的方法。 该方法包括：以迭代方式连续解码块之前临时并连续地存储块，输入存储器具有用于存储至少两个块的存储器大小，并且定义表示阈值迭代次数的当前指示 用于解码当前块。 该方法包括解码当前块直到满足解码标准，或者只要对当前块解码执行的迭代次数尚未达到当前指示，而第一后续块和第二后续块的一部分中的至少一个 被存储在输入存储器中，并且根据为解码当前块执行的迭代次数来更新当前用于解码第一后续块的指示。

公开(公告)号：US20110099448A1

公开(公告)日：2011-04-28

申请号：US12605078

申请日：2009-10-23

Applicant: TINOOSH MOHSENIN ,  Bevan Baas ,  Pascal Urard

Inventor： TINOOSH MOHSENIN ,  Bevan Baas ,  Pascal Urard

IPC: H03M13/05 ,  G06F11/10

CPC classification number: H03M13/1137 ,  H03M13/1122

Abstract: A method of decoding a low density parity check (LDPC) encoded block, with the LDPC code being defined by a parity check matrix including rows, includes processing the rows of the parity check matrix. The processing includes updating data in the rows using a split-row decoding algorithm. The updating includes partitioning each row into a plurality of partitions, and determining for each partition a first local minimum of the data of the partition. The method also includes comparing for each partition the first local minimum with a threshold, and updating at least some of the data of all partitions of the row using the local minimums or the threshold depending on the results of the comparing.

Abstract translation: 解码低密度奇偶校验（LDPC）编码块的方法，其中LDPC码由包括行的奇偶校验矩阵定义，包括处理奇偶校验矩阵的行。 该处理包括使用分行解码算法更新行中的数据。 所述更新包括将每行划分成多个分区，并且为每个分区确定该分区的数据的第一局部最小值。 该方法还包括将第一局部最小值与阈值进行比较，并根据比较结果，使用局部最小值或阈值来更新行的所有分区的至少一些数据。

公开(公告)号：US08499228B2

公开(公告)日：2013-07-30

申请号：US12914306

申请日：2010-10-28

Applicant: Vincent Heinrich ,  Pascal Urard

Inventor： Vincent Heinrich ,  Pascal Urard

IPC: H03M13/03

CPC classification number: G11B20/1803 ,  G11B2020/10759 ,  H03M13/1111 ,  H03M13/2957 ,  H03M13/3972 ,  H03M13/4146 ,  H03M13/6343 ,  H03M13/6502

Abstract: A method is for decoding a block of N information items encoded with an error correction code and mutually correlated. The method includes carrying out a first decorrelation of the N information items of a block is carried out, and storing the block decorrelated. The method also includes a performing a processing for decoding a group of P information items of the block, and decorrelating at least part of the P decoded information items. The processing for decoding the group of P information items and the decorrelation are repeated with different successive groups of P information items of the block until the N information items of the block have been processed, until a decoding criterion is satisfied.

Abstract translation: 一种方法是解码用纠错码编码并相互相关的N个信息项的块。 该方法包括执行块的N个信息项的第一去相关，并且存储相关的块。 该方法还包括执行用于解码该块的P个信息项的处理，以及对至少部分的P个解码的信息项进行解相关。 用于解码P个信息项的组合和解相关的处理被重复，直到块的N个信息项已经被处理之前的不同的连续的P个信息项组，直到满足解码标准。

公开(公告)号：US20120173947A1

公开(公告)日：2012-07-05

申请号：US12676802

申请日：2008-09-02

Applicant: Adrian Voicila ,  David Declercq ,  Marc Fossorier ,  François Verdier ,  Pascal Urard

Inventor： Adrian Voicila ,  David Declercq ,  Marc Fossorier ,  François Verdier ,  Pascal Urard

IPC: H03M13/05 ,  G06F11/10

CPC classification number: H03M13/1171 ,  H03M13/1134 ,  H03M13/114 ,  H03M13/116 ,  H03M13/118 ,  H03M13/6502

Abstract: A string of K initial symbols is encoded with a code of the parity check type. The K initial symbols belong to a Galois field of order q strictly greater than 2. The code is defined by code characteristics representable by a graph (GRH) comprising N−K first nodes (NCi), each node satisfying a parity check equation defined on the Galois field of order q, N packets of intermediate nodes (NITi) and NI second nodes (NSSi), each intermediate node being linked to a single first node and to several second nodes by way of a connection scheme. The string of K initial symbols is encoded by using the said code characteristics and a string of N encoded symbols is obtained, respectively subdivided into NI sub-symbols belonging respectively to mathematical sets whose orders are less than q, according to a subdivision scheme representative of the connection scheme (H).

Abstract translation: 一组K个初始符号用奇偶校验类型的代码编码。 K个初始符号属于严格大于2的阶数q的Galois域。该码由包含N-K个第一节点（NCi）的图形（GRH）表示的代码特征定义，每个节点满足在 阶次q的伽罗瓦域，中间节点（NITi）和NI第二节点（NSSi）的N个分组，每个中间节点通过连接方案链接到单个第一节点和多个第二节点。 通过使用所述代码特征对K个初始符号的串进行编码，并且获得一组N个编码符号，分别被分为归属于小于q的数学集的NI子符号，根据代表 连接方案（H）。

公开(公告)号：US20090031094A1

公开(公告)日：2009-01-29

申请号：US12150599

申请日：2008-04-29

Applicant: Cyrille Chavet ,  Pascal Urard ,  Philippe Coussy ,  Eric Martin

Inventor： Cyrille Chavet ,  Pascal Urard ,  Philippe Coussy ,  Eric Martin

IPC: G06F12/06 ,  G06F12/00

CPC classification number: H03M13/2775 ,  H03M13/2957 ,  H04L1/0071

Abstract: A data interleaving device is provided that includes an input, an output, and a data interleaver coupled to the input and the output. The input receives data originating from a plurality of processing blocks. The output transfers interleaved data to the plurality of processing blocks. The data interleaver includes a controller, at least one interconnection module, and a plurality of memories. The controller prepares a data-to-memory assignment data structure. The at least one interconnection module switches data in parallel according to the data-to-memory assignment data structure and acts identically on all data switched simultaneously in parallel. The plurality of memories store the switched data. The data interleaver interleaves data received from the input and provides the interleaved data at the output.

Abstract translation: 提供了一种包括耦合到输入和输出的输入，输出和数据交织器的数据交织装置。 输入接收来自多个处理块的数据。 输出将交错数据传送到多个处理块。 数据交织器包括控制器，至少一个互连模块和多个存储器。 控制器准备数据到内存分配数据结构。 至少一个互连模块根据数据到存储器分配数据结构并行地切换数据，并且对并行地同时切换的所有数据执行相同的操作。 多个存储器存储切换的数据。 数据交织器交织从输入接收的数据，并在输出端提供交错数据。

公开(公告)号：US07032165B2

公开(公告)日：2006-04-18

申请号：US10357561

申请日：2003-02-04

Applicant: Pascal Urard ,  Thierry Valentin

Inventor： Pascal Urard ,  Thierry Valentin

IPC: H03M13/03

CPC classification number: H03M13/3961 ,  H03M13/4107

Abstract: A device for implementing a function of add-compare-select type in an error correction code decoder, having first and second adders for adding, respectively for first and second branches, branch metric values, intermediate value of former state metrics, and values of former state metric offset, thus forming first and second values of present state metrics; a comparator, coupled to the first and second adders, for selecting the highest value from among the first and second values; circuitry for determining a digital value of present state metric offset including a single bit, based on the first and second values.