公开(公告)号：US20050251660A1

公开(公告)日：2005-11-10

申请号：US10840560

申请日：2004-05-06

申请人： Robert Bell ,  Thomas Capasso ,  Guy Guthrie ,  Hugh Shen ,  Jeffrey Stuecheli

发明人： Robert Bell ,  Thomas Capasso ,  Guy Guthrie ,  Hugh Shen ,  Jeffrey Stuecheli

IPC分类号： G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/3824 ,  G06F9/3861

摘要： A method and processor chip design for enabling a processor core to continue sending store operations speculatively to the store queue after the core receives indication that the store queue is full. The processor core is configured with speculative store logic that enables the processor core to continue issuing store operations while the store queue full signal is asserted. A copy of the speculatively issued store operation is placed within a speculative store buffer. The core waits for a signal from the store queue indicating the store operation was accepted into the store queue. When the speculatively-issued store operation is accepted within the store queue, the copy is discarded from the buffer. However, when the store operation is rejected, the speculative store logic re-issues the store operation ahead of normal store operations.

摘要翻译： 一种方法和处理器芯片设计，用于使得处理器核心能够在核心接收到存储队列已满的指示之后继续向商店队列发送存储操作。 处理器核心配置有推测存储逻辑，使得处理器核心能够在存储队列满信号被断言的同时继续发出存储操作。 投机发行的存储操作的副本放置在推测性存储缓冲区内。 核心等待来自存储队列的信号，指示存储操作被接受到存储队列中。 当存储队列中接受推测发出的存储操作时，该副本将从缓冲区中丢弃。 然而，当存储操作被拒绝时，推测存储逻辑在正常存储操作之前重新发布存储操作。

公开(公告)号：US08352712B2

公开(公告)日：2013-01-08

申请号：US10840560

申请日：2004-05-06

申请人： Robert H. Bell, Jr. ,  Thomas Michael Capasso ,  Guy Lynn Guthrie ,  Hugh Shen ,  Jeffrey Adam Stuecheli

发明人： Robert H. Bell, Jr. ,  Thomas Michael Capasso ,  Guy Lynn Guthrie ,  Hugh Shen ,  Jeffrey Adam Stuecheli

IPC分类号： G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/3824 ,  G06F9/3861

摘要： A method and processor chip design for enabling a processor core to continue sending store operations speculatively to the store queue after the core receives indication that the store queue is full. The processor core is configured with speculative store logic that enables the processor core to continue issuing store operations while the store queue full signal is asserted. A copy of the speculatively issued store operation is placed within a speculative store buffer. The core waits for a signal from the store queue indicating the store operation was accepted into the store queue. When the speculatively-issued store operation is accepted within the store queue, the copy is discarded from the buffer. However, when the store operation is rejected, the speculative store logic re-issues the store operation ahead of normal store operations.

摘要翻译： 一种方法和处理器芯片设计，用于使得处理器核心能够在核心接收到存储队列已满的指示之后继续向商店队列发送存储操作。 处理器核心配置有推测存储逻辑，使得处理器核心能够在存储队列满信号被断言的同时继续发出存储操作。 投机发行的存储操作的副本放置在推测性存储缓冲区内。 核心等待来自存储队列的信号，指示存储操作被接受到存储队列中。 当存储队列中接受推测发出的存储操作时，该副本将从缓冲区中丢弃。 然而，当存储操作被拒绝时，推测存储逻辑在正常存储操作之前重新发布存储操作。

公开(公告)号：US08195880B2

公开(公告)日：2012-06-05

申请号：US12424255

申请日：2009-04-15

申请人： Sanjeev Gai ,  Guy Lynn Guthrie ,  Hugh Shen ,  William John Starke

发明人： Sanjeev Gai ,  Guy Lynn Guthrie ,  Hugh Shen ,  William John Starke

IPC分类号： G06F13/00

CPC分类号： G06F12/0897 ,  G06F12/0811

摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides dual dispatch points into the data flow to the dual cache banks of the L2 cache memory.

摘要翻译： 信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。 处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。 处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。 仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 L2高速缓冲存储器包括双数据库，使得一个存储体可以执行加载操作，而另一个存储体执行存储操作。 缓存系统向数据流提供双调度点到二级高速缓冲存储器的双缓存组。

公开(公告)号：US07487397B2

公开(公告)日：2009-02-03

申请号：US11260562

申请日：2005-10-27

申请人： Walter R. Lockwood ,  Ryan J. Pennington ,  Hugh Shen ,  Kenneth L. Wright

发明人： Walter R. Lockwood ,  Ryan J. Pennington ,  Hugh Shen ,  Kenneth L. Wright

IPC分类号： G06F11/00

CPC分类号： G06F11/2236

摘要： A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect in the cache memory using the fault data, and repairing the defect by setting a fuse to reroute access requests for the location to a redundant array. The fault data may include an error syndrome and a failing address. The functional test procedure creates random cache access sequences that cause varying loads of traffic in the cache memory using a test pattern based on a random seed. The functional test procedure may be carried out after completion of a nonfunctional, built-in self test of the microprocessor which sets some of the fuses.

摘要翻译： 一种通过操作微处理器来执行利用高速缓冲存储器的功能测试程序来校正诸如高速缓存存储器的微处理器的存储阵列中的缺陷的方法，在功能测试程序期间收集跟踪阵列中的故障数据， 使用故障数据在高速缓冲存储器中定位缺陷，以及通过设置保险丝将该位置的访问请求重新路由到冗余阵列来修复缺陷。 故障数据可能包括错误综合征和故障地址。 功能测试过程创建随机高速缓存访​​问序列，其使用基于随机种子的测试模式在高速缓冲存储器中引起变化的流量负载。 功能测试程序可以在完成设置一些保险丝的微处理器的非功能性内置自检之后完成。

公开(公告)号：US20080140953A1

公开(公告)日：2008-06-12

申请号：US12033454

申请日：2008-02-19

申请人： Guy Lynn Guthrie ,  Hugh Shen ,  Derek Edward Williams

发明人： Guy Lynn Guthrie ,  Hugh Shen ,  Derek Edward Williams

IPC分类号： G06F12/00

CPC分类号： G06F9/30087 ,  G06F9/3004 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3851

摘要： A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an additional tracking bit (priority bit). The priority bit is set whenever a STCX operation is placed within the entry. During selection of an entry for dispatch by the arbitration logic, the arbitration logic scans the value of the priority bits of each eligible entry. An entry with the priority bit set is given priority in the selection process within architectural rules. That entry is then selected for dispatch as early as is possible within the established rules.

公开(公告)号：US20070277026A1

公开(公告)日：2007-11-29

申请号：US11836872

申请日：2007-08-10

申请人： ROBERT BELL ,  Hugh Shen ,  Jeffrey Stuecheli ,  Derek Williams

发明人： ROBERT BELL ,  Hugh Shen ,  Jeffrey Stuecheli ,  Derek Williams

IPC分类号： G06F9/00

CPC分类号： G06F9/3824 ,  G06F9/30043 ,  G06F12/0897

摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.

摘要翻译： 处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。 存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。 此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。

公开(公告)号：US20060184749A1

公开(公告)日：2006-08-17

申请号：US11056764

申请日：2005-02-11

申请人： Guy Guthrie ,  Hugh Shen ,  William Starke ,  Derek Williams

发明人： Guy Guthrie ,  Hugh Shen ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0831

摘要： A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is dispatched to a selector upon entering a bottom latch in the pipeline. The stall/reorder unit is not informed as to whether the dispatched snoop request is accepted by an arbitration mechanism for several clock cycles after the dispatch occurred. A copy of the dispatched snoop request is stored in a top latch in an overrun pipeline of latches in the first unit upon dispatching the snoop request. By maintaining information about the snoop request, the snoop request may be dispatched again to the selector in case the dispatched snoop request was rejected thereby increasing the chance that the snoop request will ultimately be accepted.

公开(公告)号：US20060090035A1

公开(公告)日：2006-04-27

申请号：US10970437

申请日：2004-10-21

申请人： Guy Guthrie ,  Hugh Shen ,  Derek Williams

发明人： Guy Guthrie ,  Hugh Shen ,  Derek Williams

IPC分类号： G06F12/00

CPC分类号： G06F9/30087 ,  G06F9/3004 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3851

摘要： A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an additional tracking bit (priority bit). The priority bit is set whenever a STCX operation is placed within the entry. During selection of an entry for dispatch by the arbitration logic, the arbitration logic scans the value of the priority bits of each eligible entry. An entry with the priority bit set is given priority in the selection process within architectural rules. That entry is then selected for dispatch as early as is possible within the established rules.

公开(公告)号：US08140765B2

公开(公告)日：2012-03-20

申请号：US12424228

申请日：2009-04-15

申请人： Sanjeev Gai ,  Guy Lynn Guthrie ,  Hugh Shen ,  William John Starke

发明人： Sanjeev Gai ,  Guy Lynn Guthrie ,  Hugh Shen ,  William John Starke

IPC分类号： G06F13/28

CPC分类号： G06F12/0846 ,  G06F12/0897

摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides a single dispatch point into the data flow to the dual cache banks of the L2 cache memory.

摘要翻译： 信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。 处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。 处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。 仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 L2高速缓冲存储器包括双数据库，使得一个存储体可以执行加载操作，而另一个存储体执行存储操作。 缓存系统向数据流提供单个调度点到L2缓存存储器的双缓存组。

公开(公告)号：US07840758B2

公开(公告)日：2010-11-23

申请号：US11689990

申请日：2007-03-22

申请人： Robert H. Bell, Jr. ,  Hugh Shen ,  Jeffrey Adam Stuecheli ,  Derek Edward Williams

发明人： Robert H. Bell, Jr. ,  Hugh Shen ,  Jeffrey Adam Stuecheli ,  Derek Edward Williams

IPC分类号： G06F12/00

CPC分类号： G06F9/3824 ,  G06F9/30043 ,  G06F12/0897

摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.

摘要翻译： 处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。 存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。 此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。