-
31.发明授权Method for performing a direct memory access block move in a direct memory access device 失效用于执行直接存储器访问块的方法在直接存储器访问设备中移动公开(公告)号：US07523228B2
公开(公告)日：2009-04-21
申请号：US11532562
申请日：2006-09-18
CPC分类号： G06F13/28
摘要： A direct memory access (DMA) device is structured as a loosely coupled DMA engine (DE) and a bus engine (BE). The DE breaks the programmed data block moves into separate transactions, interprets the scatter/gather descriptors, and arbitrates among channels. The DE and BE use a combined read-write (RW) command that can be queued between the DE and the BE. The bus engine (BE) has two read queues and a write queue. The first read queue is for “new reads” and the second read queue is for “old reads,” which are reads that have been retried on the bus at least once. The BE gives absolute priority to new reads, and still avoids deadlock situations.
摘要翻译： 直接存储器访问（DMA）设备被构造为松散耦合的DMA引擎（DE）和总线引擎（BE）。 DE将编程数据块移动到单独的事务中，解释分散/收集描述符，并在通道之间进行仲裁。 DE和BE使用可以在DE和BE之间排队的组合读写（RW）命令。 总线引擎（BE）具有两个读队列和一个写队列。 第一个读取队列是用于“新读取”，第二个读取队列用于“旧读取”，这是至少在总线上重试的读取。 BE绝对优先考虑新的读取，并且仍然避免死锁的情况。
-
公开(公告)号：US20080126602A1
公开(公告)日：2008-05-29
申请号：US11532562
申请日：2006-09-18
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A direct memory access (DMA) device is structured as a loosely coupled DMA engine (DE) and a bus engine (BE). The DE breaks the programmed data block moves into separate transactions, interprets the scatter/gather descriptors, and arbitrates among channels. The DE and BE use a combined read-write (RW) command that can be queued between the DE and the BE. The bus engine (BE) has two read queues and a write queue. The first read queue is for “new reads” and the second read queue is for “old reads,” which are reads that have been retried on the bus at least once. The BE gives absolute priority to new reads, and still avoids deadlock situations.
摘要翻译： 直接存储器访问（DMA）设备被构造为松散耦合的DMA引擎（DE）和总线引擎（BE）。 DE将编程数据块移动到单独的事务中，解释分散/收集描述符，并在通道之间进行仲裁。 DE和BE使用可以在DE和BE之间排队的组合读写（RW）命令。 总线引擎（BE）具有两个读队列和一个写队列。 第一个读取队列是用于“新读取”，第二个读取队列用于“旧读取”，这是至少在总线上重试的读取。 BE绝对优先考虑新的读取，并且仍然避免死锁的情况。
-
33.发明申请System and Method for Improved Logic Simulation Using a Negative Unknown Boolean State 失效使用负的未知布尔状态改进逻辑模拟的系统和方法公开(公告)号：US20080126065A1
公开(公告)日：2008-05-29
申请号：US11531708
申请日：2006-09-14
申请人： Richard Nicholas
发明人： Richard Nicholas
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A system and method for simulating a circuit design using both an unknown Boolean state and a negative unknown Boolean state is provided. When the circuit is simulated, one or more initial simulated logic elements are initialized to the unknown Boolean state. The initialized unknown Boolean states are then fed to one or more simulated logic elements and the simulator simulates the handling of the unknown Boolean state by the simulated logic elements. Examples of simulated logic elements include gates and latches, such as flip-flops, inverters, and basic logic gates. The processing results in at least one negative unknown Boolean state. An example of when a negative unknown Boolean state would result would be when the unknown Boolean state is inverted by an inverter. The resulting negative unknown Boolean state is then fed to other simulated logic elements that generate further simulation results based on processing the negative unknown Boolean state.
摘要翻译： 提供了一种用于模拟使用未知布尔状态和负未知布尔状态的电路设计的系统和方法。 当模拟电路时，一个或多个初始仿真逻辑元件被初始化为未知布尔状态。 然后将初始化的未知布尔状态馈送到一个或多个仿真逻辑元件，并且模拟器通过模拟逻辑元件模拟未知布尔状态的处理。 模拟逻辑元件的示例包括门和锁存器，例如触发器，反相器和基本逻辑门。 该处理结果至少有一个负的未知布尔状态。 当未知的布尔状态由逆变器反相时，将产生负的未知布尔状态的一个例子。 然后将所得到的负未知布尔状态馈送到其他仿真逻辑元件，该逻辑元件基于处理负未知布尔状态生成进一步的仿真结果。
-
公开(公告)号：US20080076709A1
公开(公告)日：2008-03-27
申请号：US11698250
申请日：2007-01-25
申请人： Michael Black , Martin Burnham , Jason Fedon , John Hodgson , David Knowles , Michael Lonetto , Richard Nicholas , Leslie Palmer , Julie Pratt , Raymond Reichard , Martin Rosenberg , Christopher Traini , Judith Ward , Richard Warren
发明人： Michael Black , Martin Burnham , Jason Fedon , John Hodgson , David Knowles , Michael Lonetto , Richard Nicholas , Leslie Palmer , Julie Pratt , Raymond Reichard , Martin Rosenberg , Christopher Traini , Judith Ward , Richard Warren
CPC分类号： C12N9/0036 , A61K38/00 , A61K39/00 , C07K14/31 , C07K16/1275 , C07K2319/00 , C12N9/78 , C12N15/52 , C12Q1/689 , C12Q2600/158 , C12Y105/0103 , C12Y305/04025
摘要： This invention relates to newly identified Staphylococcal polynucleotides, polypeptides encoded by such polynucleotides, the uses of such polynucleotides and polypeptides, as well as the production of such polynucleotides and polypeptides and recombinant host cells transformed with the polynucleotides. This invention also relates to inhibiting the biosynthesis or action of such polynucleotides or polypeptides and to the use of such inhibitors in therapy.
摘要翻译： 本发明涉及新鉴定的葡萄球菌多核苷酸，由这种多核苷酸编码的多肽，这种多核苷酸和多肽的用途，以及这些多核苷酸和多肽的产生以及用多核苷酸转化的重组宿主细胞。 本发明还涉及抑制这些多核苷酸或多肽的生物合成或作用以及这种抑制剂在治疗中的用途。
-
公开(公告)号：US07275199B2
公开(公告)日：2007-09-25
申请号：US10912483
申请日：2004-08-05
IPC分类号： G11C29/52
CPC分类号： G06F11/1032
摘要： A method, an apparatus, and a computer program are provided for sequentially determining parity of stored data. Because of the inherent instabilities that exist in most memory arrays, data corruption can be a substantial problem. Parity checking and other techniques are typically employed to counteract the problem. However, with parity checking and other techniques, there are tradeoffs. Time required to perform the parity check, for example, can cause system latencies. Therefore, to reduce latencies, a trusted register can be included into a memory system to allow for immediate access to one piece of trusted data. By being able to read one piece of trusted data, the system can overlap the parity checking and delivery of a location of data with the reading of the next location of data from the memory array. Hence, a full cycle of latency can be eliminated without the reduction of the clock frequency.
摘要翻译： 提供了一种方法，装置和计算机程序，用于顺序地确定存储的数据的奇偶性。 由于大多数内存阵列中存在固有的不稳定性，数据损坏可能是一个重大问题。 通常采用奇偶校验和其他技术来解决问题。 然而，通过奇偶校验和其他技术，有权衡。 例如，执行奇偶校验所需的时间可能会导致系统延迟。 因此，为了减少延迟，信任寄存器可以被包括在存储器系统中以允许立即访问一条可信数据。 通过能够读取一条可信赖的数据，系统可以通过从存储器阵列读取数据的下一个位置来重叠数据位置的奇偶校验和传送。 因此，可以消除整个周期的延迟，而不降低时钟频率。
-
公开(公告)号：US20060174068A1
公开(公告)日：2006-08-03
申请号：US11050295
申请日：2005-02-03
申请人： Bernard Drerup , Richard Nicholas , Barry Wolford
发明人： Bernard Drerup , Richard Nicholas , Barry Wolford
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method, and bus prefetching mechanism are provided for implementing enhanced buffer control. A computer system includes a plurality of masters and at least one slave exchanging data over a system bus and the slave prefetches read data under control of a master. The master generates a continue bus signal that indicates a new or a continued request. The master generates a prefetch bus signal that indicates an amount to prefetch including no prefetching. The master includes a mechanism for continuing a sequence of reads allowing prefetching until a request is made indicating a prefetch amount of zero.
-
公开(公告)号：US06174705B1
公开(公告)日：2001-01-16
申请号：US09425665
申请日：1999-10-22
IPC分类号： C12N121
CPC分类号： C07K14/40
摘要： The invention provides ARO1 polypeptides and DNA (RNA) encoding such ARO1 and a procedure for producing such polypeptides by recombinant techniques. Also provided are methods for utilizing such ARO1 for the treatment of infection, particularly fungal infections. Antagonists against such ARO1 and their use as a therapeutic to treat infections, particularly fungal infections are also provided. Further provided are diagnostic assays for detecting diseases related to the presence of ARO1 nucleic acid sequences and the polypeptides in a host. Also provided are diagnostic assays for detecting polynucleotides encoding arom and for detecting the polypeptide in a host.
摘要翻译： 本发明提供ARO1多肽和编码这种ARO1的DNA（RNA），以及通过重组技术产生此类多肽的方法。 还提供了利用这种ARO1来治疗感染，特别是真菌感染的方法。 还提供了抗这种ARO1的拮抗剂及其作为治疗感染的用途，特别是真菌感染。 还提供了用于检测与宿主中ARO1核酸序列和多肽的存在相关的疾病的诊断测定法。 还提供了用于检测编码芳香和用于在宿主中检测多肽的多核苷酸的诊断测定法。
-
公开(公告)号：USD696524S1
公开(公告)日：2013-12-31
申请号：US29421742
申请日：2012-09-12
申请人： Ali Ersan , Richard Nicholas , John McKeever
设计人： Ali Ersan , Richard Nicholas , John McKeever
-
39.发明授权System and method for improved logic simulation using a negative unknown boolean state 失效使用负的未知布尔状态改进逻辑仿真的系统和方法公开(公告)号：US07761277B2
公开(公告)日：2010-07-20
申请号：US11531708
申请日：2006-09-14
申请人： Richard Nicholas
发明人： Richard Nicholas
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A system and method for simulating a circuit design using both an unknown Boolean state and a negative unknown Boolean state is provided. When the circuit is simulated, one or more initial simulated logic elements are initialized to the unknown Boolean state. The initialized unknown Boolean states are then fed to one or more simulated logic elements and the simulator simulates the handling of the unknown Boolean state by the simulated logic elements. Examples of simulated logic elements include gates and latches, such as flip-flops, inverters, and basic logic gates. The processing results in at least one negative unknown Boolean state. An example of when a negative unknown Boolean state would result would be when the unknown Boolean state is inverted by an inverter. The resulting negative unknown Boolean state is then fed to other simulated logic elements that generate further simulation results based on processing the negative unknown Boolean state.
摘要翻译： 提供了一种用于模拟使用未知布尔状态和负未知布尔状态的电路设计的系统和方法。 当模拟电路时，一个或多个初始仿真逻辑元件被初始化为未知布尔状态。 然后将初始化的未知布尔状态馈送到一个或多个仿真逻辑元件，并且模拟器通过模拟逻辑元件模拟未知布尔状态的处理。 模拟逻辑元件的示例包括门和锁存器，例如触发器，反相器和基本逻辑门。 处理结果至少有一个负的未知布尔状态。 当未知的布尔状态由逆变器反相时，将产生负的未知布尔状态的一个例子。 然后将所得到的负未知布尔状态馈送到其他仿真逻辑元件，该逻辑元件基于处理负未知布尔状态生成进一步的仿真结果。
-
40.发明授权公开(公告)号：US07620749B2
公开(公告)日：2009-11-17
申请号：US11621789
申请日：2007-01-10
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A DMA device prefetches descriptors into a descriptor prefetch buffer. The size of descriptor prefetch buffer holds an appropriate number of descriptors for a given latency environment. To support a linked list of descriptors, the DMA engine prefetches descriptors based on the assumption that they are sequential in memory and discards any descriptors that are found to violate this assumption. The DMA engine seeks to keep the descriptor prefetch buffer full by requesting multiple descriptors per transaction whenever possible. The bus engine fetches these descriptors from system memory and writes them to the prefetch buffer. The DMA engine may also use an aggressive prefetch where the bus engine requests the maximum number of descriptors that the buffer will support whenever there is any space in the descriptor prefetch buffer. The DMA device discards any remaining descriptors that cannot be stored.
摘要翻译： DMA设备将描述符预取到描述符预取缓冲区中。 描述符预取缓冲区的大小在给定的等待时间环境中保存适当数量的描述符。 为了支持描述符的链表，DMA引擎基于它们在存储器中是连续的假设来预取描述符，并丢弃任何被发现违反这个假设的描述符。 DMA引擎寻求通过每个事务请求多个描述符尽可能地保持描述符预取缓冲区已满。 总线引擎从系统内存中读取这些描述符，并将它们写入预取缓冲区。 DMA引擎还可以使用积极的预取，其中总线引擎请求缓冲区将在描述符预取缓冲器中存在任何空间时将支持的最大数量的描述符。 DMA设备丢弃任何其他不能存储的描述符。
-
-
-
-
-
-
-
-
-
搜索结果
54 条记录 (耗时 0.03 秒)
