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公开(公告)号：US07275199B2
公开(公告)日：2007-09-25
申请号：US10912483
申请日：2004-08-05
IPC分类号： G11C29/52
CPC分类号： G06F11/1032
摘要： A method, an apparatus, and a computer program are provided for sequentially determining parity of stored data. Because of the inherent instabilities that exist in most memory arrays, data corruption can be a substantial problem. Parity checking and other techniques are typically employed to counteract the problem. However, with parity checking and other techniques, there are tradeoffs. Time required to perform the parity check, for example, can cause system latencies. Therefore, to reduce latencies, a trusted register can be included into a memory system to allow for immediate access to one piece of trusted data. By being able to read one piece of trusted data, the system can overlap the parity checking and delivery of a location of data with the reading of the next location of data from the memory array. Hence, a full cycle of latency can be eliminated without the reduction of the clock frequency.
摘要翻译： 提供了一种方法，装置和计算机程序，用于顺序地确定存储的数据的奇偶性。 由于大多数内存阵列中存在固有的不稳定性，数据损坏可能是一个重大问题。 通常采用奇偶校验和其他技术来解决问题。 然而，通过奇偶校验和其他技术，有权衡。 例如，执行奇偶校验所需的时间可能会导致系统延迟。 因此，为了减少延迟，信任寄存器可以被包括在存储器系统中以允许立即访问一条可信数据。 通过能够读取一条可信赖的数据，系统可以通过从存储器阵列读取数据的下一个位置来重叠数据位置的奇偶校验和传送。 因此，可以消除整个周期的延迟，而不降低时钟频率。
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公开(公告)号：US07129769B2
公开(公告)日：2006-10-31
申请号：US11060355
申请日：2005-02-17
IPC分类号： H01H37/76
摘要： A method and apparatus are provided for protecting electronic fuse (eFuse) information. A current balancing circuit is provided that maintains a constant current demand on the eFuse voltage supply that is sufficient to blow an eFuse. Normally the constant current is applied to a semiconductor core. When an eFuse is being blown, the constant current is diverted away from the core to the eFuse and as the eFuse blows, the constant current is again dumped to the semiconductor core. Thus, a change in current due to the transient of the eFuse being blown is not detectable and the information that an eFuse has been blown is kept secure.
摘要翻译： 提供了一种用于保护电子熔丝（eFuse）信息的方法和装置。 提供了一种电流平衡电路，其对足以吹入eFuse的eFuse电压源保持恒定的电流需求。 通常，将恒定电流施加到半导体芯。 当eFuse被吹制时，恒定电流从核心转移到eFuse，并且当eFuse烧断时，恒定电流再次被转移到半导体核心。 因此，由于eFuse的瞬态被吹过而导致的电流变化是不可检测的，并且eFuse已经被熔断的信息保持安全。
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公开(公告)号：US07716546B2
公开(公告)日：2010-05-11
申请号：US11866787
申请日：2007-10-03
CPC分类号： G06F11/27
摘要： A method for improved Logic Built-In Self-Test (LBIST) includes providing a plurality of control signal sets, by an LBIST controller, to an LBIST domain comprising a plurality of LBIST satellite modules. Each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves the LBIST channel scan and LBIST sequence operations for each of the LBIST satellite modules, through the plurality of control signal sets.A test system includes a Logic Built-In Self-Test (LBIST) domain comprising a plurality of LBIST satellite modules. An LBIST controller couples to the LBIST domain and provides a plurality of control signal sets to the LBIST domain, wherein each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves LBIST channel scan operations for each of the LBIST satellite modules, through the plurality of control signal sets.
摘要翻译： 一种用于改进逻辑内置自检（LBIST）的方法包括：由LBIST控制器将多个控制信号组提供给包括多个LBIST卫星模块的LBIST域。 多个LBIST卫星模块中的每一个接收多个控制信号组中的一个。 LBIST控制器通过多个控制信号组来交织每个LBIST卫星模块的LBIST信道扫描和LBIST序列操作。 测试系统包括包括多个LBIST卫星模块的逻辑内置自测（LBIST）域。 LBIST控制器耦合到LBIST域并向LBIST域提供多个控制信号组，其中多个LBIST卫星模块中的每一个接收多个控制信号组中的一个。 LBIST控制器通过多个控制信号组来交织每个LBIST卫星模块的LBIST信道扫描操作。
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4.发明授权Electronic fuse apparatus and methodology including addressable virtual electronic fuses 有权电子熔断装置和方法，包括可寻址的虚拟电子保险丝公开(公告)号：US07515498B2
公开(公告)日：2009-04-07
申请号：US11674227
申请日：2007-02-13
IPC分类号： G11C7/00
摘要： A virtual electronic fuse (VEF) apparatus and methodology are disclosed that permit the state of an electronic fuse to change from an un-blown state to a blown state and then back to a virtual un-blown state. In one embodiment, the electronic fuse may change from the virtual un-blown state back again to a virtual blown state. The fuse apparatus includes multiple VEFs, each VEF exhibiting a respective address. The fuse apparatus also includes an address pool including multiple address pool locations. A fuse programmer stores an address of one of the VEFs in one or more address pool locations to indicate one or more state changes for a particular VEF. The fuse programmer may also store different VEF addresses in different address pool locations to indicate state changes for different VEFs.
摘要翻译： 公开了一种虚拟电子熔丝（VEF）装置和方法，其允许电子熔丝的状态从未吹制状态改变到吹制状态，然后返回到虚拟未吹塑状态。 在一个实施例中，电子熔断器可以从虚拟未发生状态改变回到虚拟吹制状态。 熔丝装置包括多个VEF，每个VEF呈现相应的地址。 熔丝装置还包括包括多个地址池位置的地址池。 保险丝编程器将一个VEF的地址存储在一个或多个地址池位置中，以指示特定VEF的一个或多个状态改变。 保险丝编程器还可以在不同的地址池位置存储不同的VEF地址，以指示不同VEF的状态变化。
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5.发明授权Method and apparatus for determining system identification number system using system data bus and pull-up resistors in combination with a sensing circuitry 失效用于使用系统数据总线和上拉电阻器与感测电路组合来确定系统识别号码系统的方法和装置
公开(公告)号：US5987548A
公开(公告)日：1999-11-16
申请号：US888800
申请日：1997-07-07
CPC分类号： G06F13/4068
摘要： A method and implementing system are provided for determining and retaining an identification number relevant to an electronic system component and/or component configuration. In an exemplary embodiment, existing pull-up resistors within a computer system are connected in a manner to enable associated circuitry to determine a pre-assigned identification number for the computer system. The identification number is stored in an identification number register and accessible for providing the identification number in response to a requests from other devices within the system.
摘要翻译： 提供了一种用于确定和保留与电子系统组件和/或组件配置相关的识别号的方法和实现系统。 在示例性实施例中，计算机系统内的现有上拉电阻器以使得相关联的电路能够确定计算机系统的预先分配的识别号码的方式被连接。 识别号码存储在识别号码寄存器中，并可被访问以便响应来自系统内其他设备的请求提供识别号码。
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公开(公告)号：US20090094496A1
公开(公告)日：2009-04-09
申请号：US11866787
申请日：2007-10-03
IPC分类号： G06F11/25
CPC分类号： G06F11/27
摘要： A method for improved Logic Built-In Self-Test (LBIST) includes providing a plurality of control signal sets, by an LBIST controller, to an LBIST domain comprising a plurality of LBIST satellite modules. Each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves the LBIST channel scan and LBIST sequence operations for each of the LBIST satellite modules, through the plurality of control signal sets.A test system includes a Logic Built-In Self-Test (LBIST) domain comprising a plurality of LBIST satellite modules. An LBIST controller couples to the LBIST domain and provides a plurality of control signal sets to the LBIST domain, wherein each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves LBIST channel scan operations for each of the LBIST satellite modules, through the plurality of control signal sets.
摘要翻译： 一种用于改进逻辑内置自检（LBIST）的方法包括：由LBIST控制器将多个控制信号组提供给包括多个LBIST卫星模块的LBIST域。 多个LBIST卫星模块中的每一个接收多个控制信号组中的一个。 LBIST控制器通过多个控制信号组来交织每个LBIST卫星模块的LBIST信道扫描和LBIST序列操作。 测试系统包括包括多个LBIST卫星模块的逻辑内置自测（LBIST）域。 LBIST控制器耦合到LBIST域并向LBIST域提供多个控制信号组，其中多个LBIST卫星模块中的每一个接收多个控制信号组中的一个。 LBIST控制器通过多个控制信号组来交织每个LBIST卫星模块的LBIST信道扫描操作。
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7.发明授权公开(公告)号：US07266463B2
公开(公告)日：2007-09-04
申请号：US11126120
申请日：2005-05-10
IPC分类号： G01R19/00
CPC分类号： G01R31/3167 , G01R31/31924
摘要： An apparatus, a method, and a computer program product are provided for identifying signals in analogue electrical systems. The ID select signals that control the timing of this signal identification circuit comprise sequential numbers that count up and identify a corresponding signal. The signals to be identified are located on a group of input/output (I/O) pins. One multiplexer (first) selects a specific I/O pin in response to the ID select signals. An isolated voltage source is connected to this multiplexer and provides the selected signal to another multiplexer (second). The second multiplexer switches from this isolated voltage source to ground potential in response to the ID select signals. The isolated voltage source floats at the DC level of the selected I/O driver pin. Therefore, by connecting to the selected signal's I/O pin and the output of the second multiplexer, the selected signal can be identified and then probed.
摘要翻译： 提供了用于识别模拟电气系统中的信号的装置，方法和计算机程序产品。 控制该信号识别电路的定时的ID选择信号包括向上计数并识别相应信号的顺序号码。 要识别的信号位于一组输入/输出（I / O）引脚上。 一个多路复用器（第一）响应于ID选择信号选择一个特定的I / O引脚。 隔离电压源连接到该多路复用器，并将所选择的信号提供给另一个多路复用器（第二）。 响应于ID选择信号，第二多路复用器从该隔离电压源切换到接地电位。 隔离电压源浮动在所选I / O驱动器引脚的直流电平上。 因此，通过连接到所选信号的I / O引脚和第二多路复用器的输出，可以识别所选择的信号，然后探测。
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8.发明授权公开(公告)号：US06820226B2
公开(公告)日：2004-11-16
申请号：US10042097
申请日：2002-01-07
IPC分类号： G01R3128
CPC分类号： G06F11/26 , G01R31/31924
摘要： In one aspect of the invention, a method for testing includes interposing a tester between first and second logic. The first logic and second logic have respective first and second output drivers. The tester operates in test cycles to detect dynamic contention responsive to a signal asserted by the first driver during one of the test cycles and a signal asserted by the second driver during an immediately succeeding one of the test cycles. Static contention is detected responsive to a signal asserted by the first driver during one of the test cycles and a signal asserted by the second driver during the same one of the test cycles.
摘要翻译： 在本发明的一个方面，一种用于测试的方法包括在第一和第二逻辑之间插入测试器。 第一逻辑和第二逻辑具有相应的第一和第二输出驱动器。 测试仪在测试周期中操作以响应于在一个测试周期期间由第一驱动器所确定的信号和在紧随其后的一个测试周期期间由第二驱动器断言的信号来检测动态争用。 在一个测试周期期间响应于由第一驱动器确定的信号来检测静态争用，以及在同一个测试周期期间由第二驱动器断言的信号。
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公开(公告)号：US06496911B1
公开(公告)日：2002-12-17
申请号：US09165954
申请日：1998-10-02
IPC分类号： G06F1200
CPC分类号： G06F13/4239 , G06F13/4072
摘要： An apparatus and method for memory bus tuning are implemented. A plurality of drivers having a plurality of selectable drive levels are coupled to a memory bus. The memory bus is connected to a memory device which may have a variable amount of memory, which may be in the form of dual-in-line memory modules (DIMM). A drive level is selected in response to a determination of the amount of memory included in the memory device. A register operable for receiving a data value corresponding to the amount of memory is coupled to the drivers, the drive level being selected thereby.
摘要翻译： 实现用于存储器总线调谐的装置和方法。 具有多个可选驱动电平的多个驱动器耦合到存储器总线。 存储器总线连接到可能具有可变量的存储器的存储器件，存储器可以是双列直插存储器模块（DIMM）的形式。 响应于确定包括在存储器件中的存储器的量来选择驱动器电平。 可操作用于接收与存储器量相对应的数据值的寄存器耦合到驱动器，从而选择驱动级。
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公开(公告)号：US6125467A
公开(公告)日：2000-09-26
申请号：US63962
申请日：1998-04-21
IPC分类号： G06F11/10
CPC分类号： G06F11/1012 , G06F11/1052
摘要： A method of passing transmissions through an error-correction code (ECC) block in a communications path of a computer system. The communications path interconnects a first component of the computer system (such as a random-access memory (RAM) device) and a second component of the computer system (such as a central processing unit (CPU)) using a first granularity, and a third component (such as a read-only memory (ROM) device) is further connected to the communications path such that the third component may transmit data to the second component using a second granularity which is smaller than the first granularity. The data from the third component passes through the ECC block by merging data from the third component with predefined data to present a merged data word to the ECC circuit, wherein the merged data word has the first granularity. The first granularity may be, e.g., 72 bits, while the second granularity is 8 bits. The undriven check bits and undriven data bits are preferably forced to the predefined state using a plurality of respective pull-up resistors.
摘要翻译： 一种在计算机系统的通信路径中传送通过纠错码（ECC）块的方法。 通信路径使用第一粒度将计算机系统的第一组件（诸如随机存取存储器（RAM）设备）和计算机系统的第二组件（诸如中央处理单元（CPU））互连，并且 第三组件（例如只读存储器（ROM）设备）进一步连接到通信路径，使得第三组件可以使用小于第一粒度的第二粒度将数据发送到第二组件。 来自第三组件的数据通过将来自第三组件的数据与预定义数据合并，将合并的数据字呈现给ECC电路，其中合并的数据字具有第一粒度。 第一粒度可以是例如72位，而第二粒度可以是8位。 优先使用多个相应的上拉电阻将未驱动的校验位和未驱动的数据位强制为预定状态。
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