公开(公告)号：US08397029B2

公开(公告)日：2013-03-12

申请号：US11959793

申请日：2007-12-19

Applicant: Richard Nicholas ,  Jason Alan Cox ,  Robert John Dorsey ,  Hien Minh Le ,  Eric Francis Robinson ,  Thuong Quang Truong

Inventor： Richard Nicholas ,  Jason Alan Cox ,  Robert John Dorsey ,  Hien Minh Le ,  Eric Francis Robinson ,  Thuong Quang Truong

IPC: G06F12/00

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/084

Abstract: A method for maintaining cache coherency operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache, and each PU coupled to at least another one of the plurality of PUs. A first PU receives a first data block for storage in a first cache of the first PU. The first PU stores the first data block in the first cache. The first PU assigns a first coherency state and a first tag to the first data block, wherein the first coherency state is one of a plurality of coherency states that indicate whether the first PU has accessed the first data block. The plurality of coherency states further indicate whether, in the event the first PU has not accessed the first data block, the first PU received the first data block from a neighboring PU.

Abstract translation: 用于维持高速缓存一致性的方法在具有系统存储器和多个处理单元（PU）的数据处理系统中操作，每个PU具有高速缓存，并且每个PU耦合到多个PU中的至少另一个。 第一PU接收用于存储在第一PU的第一高速缓存中的第一数据块。 第一个PU将第一个数据块存储在第一个缓存中。 第一PU将第一相关性状态和第一标签分配给第一数据块，其中第一相关性状态是指示第一PU是否已经访问了第一数据块的多个相关性状态之一。 多个相关性状态还指示在第一PU未访问第一数据块的情况下，第一PU从相邻PU接收到第一数据块。

公开(公告)号：US08150672B2

公开(公告)日：2012-04-03

申请号：US12192309

申请日：2008-08-15

Applicant: Richard Nicholas

Inventor： Richard Nicholas

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: A system and method for simulating a circuit design using both an unknown Boolean state and a negative unknown Boolean state is provided. When the circuit is simulated, one or more initial simulated logic elements are initialized to the unknown Boolean state. The initialized unknown Boolean states are then fed to one or more simulated logic elements and the simulator simulates the handling of the unknown Boolean state by the simulated logic elements. Examples of simulated logic elements include gates and latches, such as flip-flops, inverters, and basic logic gates. The processing results in at least one negative unknown Boolean state. An example of when a negative unknown Boolean state would result would be when the unknown Boolean state is inverted by an inverter. The resulting negative unknown Boolean state is then fed to other simulated logic elements that generate further simulation results based on processing the negative unknown Boolean state.

Abstract translation: 提供了一种用于模拟使用未知布尔状态和负未知布尔状态的电路设计的系统和方法。 当模拟电路时，一个或多个初始仿真逻辑元件被初始化为未知布尔状态。 然后将初始化的未知布尔状态馈送到一个或多个仿真逻辑元件，并且模拟器通过模拟逻辑元件模拟未知布尔状态的处理。 模拟逻辑元件的示例包括门和锁存器，例如触发器，反相器和基本逻辑门。 处理结果至少有一个负的未知布尔状态。 当未知的布尔状态由逆变器反相时，将产生负的未知布尔状态的一个例子。 然后将所得到的负未知布尔状态馈送到其他仿真逻辑元件，该逻辑元件基于处理负未知布尔状态生成进一步的仿真结果。

公开(公告)号：US08127106B2

公开(公告)日：2012-02-28

申请号：US12105464

申请日：2008-04-18

Applicant: Richard Nicholas ,  Eric E. Retter ,  Jeffrey A. Stuecheli

Inventor： Richard Nicholas ,  Eric E. Retter ,  Jeffrey A. Stuecheli

IPC: G06F12/00 ,  G06F9/26 ,  G06F9/34

CPC classification number: G06F12/0862 ,  G06F12/0831 ,  Y02D10/13

Abstract: An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a domain indicator in the data request indicates that the cache line corresponding to the data has a special invalid state or not. In particular, a first address and a domain indicator are extracted from first data request. The first address is used to select a finite state machine (FSM) of a memory controller based on memory regions associated with the FSMs of the memory controller. Speculative retrieval of data for the first data request from main memory is controlled based on whether the domain indicator identifies the special invalid state or not and, if the domain indicator identifies that the cache line does not have the special invalid state, based on information stored in registers associated with the selected FSM.

Abstract translation: 接入推测预测器可以基于数据请求中的域指示符是否指示对应于该数据的高速缓存行具有特殊的无效状态来预测是否对来自主存储器的数据请求的数据进行推测检索。 特别地，从第一数据请求中提取第一地址和域指示符。 第一个地址用于基于与存储器控制器的FSM相关联的存储器区域来选择存储器控制器的有限状态机（FSM）。 基于域指示符是否识别特殊无效状态来控制来自主存储器的第一数据请求的数据的推测检索，并且如果域指示符基于存储的信息识别出高速缓存行不具有特殊无效状态 在与所选FSM相关联的寄存器中。

公开(公告)号：US07865644B2

公开(公告)日：2011-01-04

申请号：US11927911

申请日：2007-10-30

Applicant: Bernard Charles Drerup ,  Richard Nicholas ,  Prasanna Srinivasan

Inventor： Bernard Charles Drerup ,  Richard Nicholas ,  Prasanna Srinivasan

IPC: G06F13/00

CPC classification number: G06F13/385

Abstract: In a method and apparatus associated with a bus controller, a set of mechanisms are selectively added to the bus controller, as well as to slave devices connected to the bus controller. A mechanism is also added to one or more master devices connected to the bus controller, in order to provide the master devices with a transaction ordering capability. The added mechanisms collectively achieve the objective of supporting connection of multiple slave devices to a common controller interface, and at the same time allowing pipelined operation of the slave devices. One embodiment of the invention is directed to a method for use with a bus and an associated bus controller, wherein the bus controller has respective master and slave interfaces for use in selectively interconnecting master devices and slave devices. The method comprises the steps of connecting one or more of the master devices to one of the master interfaces, and connecting each of a plurality of slave devices to the same one of the slave interfaces. The method further comprises operating a connected master device to send multiple commands to a selected one of the connected slave devices in accordance with a command pipelining procedure.

Abstract translation: 在与总线控制器相关联的方法和装置中，一组机制被选择性地添加到总线控制器以及连接到总线控制器的从设备。 为了向主设备提供事务排序能力，还将一种机制添加到连接到总线控制器的一个或多个主设备中。 所附加的机制共同实现支持多个从设备连接到公共控制器接口的目的，并且同时允许从设备的流水线操作。 本发明的一个实施例涉及一种与总线和相关联的总线控制器一起使用的方法，其中总线控制器具有用于选择性地互连主设备和从设备的主和从接口。 该方法包括以下步骤：将一个或多个主设备连接到一个主接口，并将多个从设备中的每一个连接到同一个从接口。 该方法还包括操作连接的主设备，以根据命令流水线过程向连接的从设备中的所选一个发送多个命令。

公开(公告)号：US07668996B2

公开(公告)日：2010-02-23

申请号：US11877296

申请日：2007-10-23

Applicant: Bernard C. Drerup ,  Richard Nicholas

Inventor： Bernard C. Drerup ,  Richard Nicholas

IPC: G06F13/36 ,  G06F13/00 ,  H04L12/28

CPC classification number: G06F13/364

Abstract: An improved method, device and data processing system are presented. In one embodiment, the method includes a source device sending a request for a bus grant to deliver data to a data bus connecting a source device and a destination device. The device receives the bus grant and logic within the device determines whether the bandwidth of the data bus allocated to the bus grant will be filled by the data. If the bandwidth of the data bus allocated to the bus grant will not be filled by the data, the device appends additional data to the first data and delivers the combined data to the data bus during the bus grant for the first data. When the bandwidth of the data bus allocated to the bus grant will be filled by the first data, the device delivers only the first data to the data bus during the bus grant.

Abstract translation: 提出了一种改进的方法，设备和数据处理系统。 在一个实施例中，该方法包括发送对总线许可的请求的源设备，以向连接源设备和目的地设备的数据总线传送数据。 设备接收总线许可，并且设备内的逻辑确定分配给总线授权的数据总线的带宽是否将被数据填充。 如果分配给总线授权的数据总线的带宽不会被数据填充，则设备将附加数据附加到第一个数据，并在第一个数据的总线授权期间将组合的数据传送到数据总线。 当分配给总线授权的数据总线的带宽将由第一个数据填充时，设备在总线授权期间只将第一个数据传送到数据总线。

公开(公告)号：US20090327612A1

公开(公告)日：2009-12-31

申请号：US12105464

申请日：2008-04-18

Applicant: Richard Nicholas ,  Eric E. Retter ,  Jeffrey A. Stuecheli

Inventor： Richard Nicholas ,  Eric E. Retter ,  Jeffrey A. Stuecheli

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0862 ,  G06F12/0831 ,  Y02D10/13

Abstract: An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a domain indicator in the data request indicates that the cache line corresponding to the data has a special invalid state or not. In particular, a first address and a domain indicator are extracted from first data request. The first address is used to select a finite state machine (FSM) of a memory controller based on memory regions associated with the FSMs of the memory controller. Speculative retrieval of data for the first data request from main memory is controlled based on whether the domain indicator identifies the special invalid state or not and, if the domain indicator identifies that the cache line does not have the special invalid state, based on information stored in registers associated with the selected FSM.

Abstract translation: 接入推测预测器可以基于数据请求中的域指示符是否指示对应于该数据的高速缓存行具有特殊的无效状态来预测是否对来自主存储器的数据请求的数据进行推测检索。 特别地，从第一数据请求中提取第一地址和域指示符。 第一个地址用于基于与存储器控制器的FSM相关联的存储器区域来选择存储器控制器的有限状态机（FSM）。 基于域指示符是否识别特殊无效状态来控制来自主存储器的第一数据请求的数据的推测检索，并且如果域指示符基于存储的信息识别出高速缓存行不具有特殊无效状态 在与所选FSM相关联的寄存器中。

公开(公告)号：US20080162771A1

公开(公告)日：2008-07-03

申请号：US12048772

申请日：2008-03-14

Applicant: Richard Nicholas

Inventor： Richard Nicholas

IPC: G06F13/36

CPC classification number: G06F13/362

Abstract: A circuit arrangement for bus arbitration alters the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence. To this end, an arbiter grants access to a first group of devices according to a predetermined sequence. The arbiter then automatically alters the sequence for a second group of devices, granting access to the bus for the second group according to the altered sequence. These features allow the order in which the arbiter sequences through the groups to be automatically varied with respect to each other, diminishing the likelihood of lockout.

Abstract translation: 用于总线仲裁的电路装置改变设备请求相对于彼此和先前的仲裁序列被仲裁的顺序。 为此，仲裁器根据预定的顺序授予对第一组设备的访问。 仲裁器然后自动改变第二组设备的序列，根据改变的顺序授予对第二组总线的访问。 这些特征允许通过组的仲裁器序列相对于彼此自动变化的顺序，减少锁定的可能性。

公开(公告)号：US06346405B1

公开(公告)日：2002-02-12

申请号：US09685668

申请日：2000-10-10

Applicant: Rebecca Greenwood ,  Richard Nicholas

Inventor： Rebecca Greenwood ,  Richard Nicholas

IPC: C12N900

CPC classification number: C07K14/40

Abstract: The invention provides ARO1 polypeptides and DNA (RNA) encoding such ARO1 and a procedure for producing such polypeptides by recombinant techniques. Also provided are methods for utilizing such ARO1 for the treatment of infection, particularly fungal infections. Antagonists against such ARO1 and their use as a therapeutic to treat infections, particularly fungal infections are also provided. Further provided are diagnostic assays for detecting diseases related to the presence of ARO1 nucleic acid sequences and the polypeptides in a host. Also provided are diagnostic assays for detecting polynucleotides encoding arom and for detecting the polypeptide in a host.

Abstract translation: 本发明提供ARO1多肽和编码这种ARO1的DNA（RNA），以及通过重组技术产生此类多肽的方法。 还提供了利用这种ARO1来治疗感染，特别是真菌感染的方法。 还提供了抗这种ARO1的拮抗剂及其作为治疗感染的用途，特别是真菌感染。 还提供了用于检测与宿主中ARO1核酸序列和多肽的存在相关的疾病的诊断测定法。 还提供了用于检测编码芳香和用于在宿主中检测多肽的多核苷酸的诊断测定法。

公开(公告)号：US08949694B2

公开(公告)日：2015-02-03

申请号：US13241598

申请日：2011-09-23

Applicant: Richard Nicholas

Inventor： Richard Nicholas

IPC: G11C29/00 ,  H03M13/00 ,  G06F11/10

CPC classification number: G06F11/1076 ,  G06F11/1016 ,  H03M13/05

Abstract: Address error detection including a method that receives write data and a write address, the write address corresponding to a location in a memory. Error correction code (ECC) bits are generated based on the received write data. The write data is transformed at a computer based on the write address and the write data, to produce transformed write data. The transforming is configured to cause an ECC to detect an address error during a read operation to the write address in response to a mismatch between either the write address or the read address and data read from the location. The transformed write data and the ECC bits are written to the location in memory.

Abstract translation: 地址错误检测，包括接收写入数据和写入地址的方法，写入地址对应于存储器中的位置。 基于接收到的写入数据生成纠错码（ECC）位。 基于写入地址和写入数据在计算机上变换写入数据，以产生变换的写入数据。 变换被配置为响应于写入地址或读取地址与从该位置读取的数据之间的不匹配，使得ECC在读取操作期间检测到写入地址的地址错误。 转换的写入数据和ECC位被写入存储器中的位置。

公开(公告)号：US08131974B2

公开(公告)日：2012-03-06

申请号：US12105427

申请日：2008-04-18

Applicant: Richard Nicholas ,  Ram Raghavan ,  Eric E. Retter ,  Jeffrey A. Stuecheli

Inventor： Richard Nicholas ,  Ram Raghavan ,  Eric E. Retter ,  Jeffrey A. Stuecheli

IPC: G06F12/00 ,  G06F9/26 ,  G06F9/34

CPC classification number: G06F12/0862 ,  G06F12/0831 ,  G06F2212/507 ,  G06F2212/6022 ,  G06F2212/6024 ,  Y02D10/13

Abstract: An access speculation predictor is provided that may be implemented using idle command processing resources, such as registers of idle finite state machines (FSMs) in a memory controller. The access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory of the data processing system based on history information stored for a memory region targeted by the data request. In particular, a first address may be extracted from the data request and compared to memory regions associated with second addresses stored in address registers of a plurality of FSMs of the memory controller. A FSM whose memory region includes the first address may be selected. History information for the memory region may be obtained from the selected FSM. The history information may be used to control whether to speculatively retrieve the data for the data request from a main memory.

Abstract translation: 提供了可以使用诸如存储器控制器中的空闲有限状态机（FSM）的寄存器的空闲命令处理资源来实现的访问推测预测器。 访问推测预测器可以基于针对数据请求所针对的存储区域存储的历史信息来预测是否对数据处理系统的主存储器执行针对数据请求的数据的推测检索。 特别地，可以从数据请求中提取第一地址，并与存储在存储器控制器的多个FSM的地址寄存器中的第二地址相关联的存储器区域进行比较。 可以选择其存储区域包括第一地址的FSM。 可以从所选择的FSM获得用于存储器区域的历史信息。 历史信息可以用于控制是否从主存储器推测性地检索数据请求的数据。