公开(公告)号：US08060027B2

公开(公告)日：2011-11-15

申请号：US12721930

申请日：2010-03-11

申请人： Khurram Muhammad ,  Dirk Leipold

发明人： Khurram Muhammad ,  Dirk Leipold

IPC分类号： H04B1/38

CPC分类号： H03C5/00 ,  H04B1/525 ,  H04B1/707

摘要： The present invention provides an RF transmission leakage mitigator for use with a full-duplex, wireless transceiver. In one embodiment, the RF transmission leakage mitigator includes an inversion generator configured to provide an RF transmission inversion signal of an interfering transceiver RF transmission to a receiving portion of the transceiver thereby creating a residual leakage signal. Additionally, the RF transmission leakage mitigator also includes a residual processor coupled to the inversion generator and configured to adjust the RF transmission inversion signal of the interfering transceiver RF transmission based on reducing the residual leakage signal to a specified level.

摘要翻译： 本发明提供了一种与全双工无线收发器一起使用的RF传输泄漏缓解器。 在一个实施例中，RF传输泄漏减轻器包括反相发生器，其被配置为将干扰收发器RF传输的RF发射反转信号提供给收发器的接收部分，从而产生残余泄漏信号。 此外，RF传输泄漏缓解器还包括耦合到反向发生器并被配置为基于将剩余泄漏信号减小到指定电平来调整干扰收发器RF传输的RF发射反转信号的残余处理器。

公开(公告)号：US20080227424A1

公开(公告)日：2008-09-18

申请号：US11717563

申请日：2007-03-13

申请人： Khurram Muhammad ,  Meng-Chang Lee ,  Dirk Leipold

发明人： Khurram Muhammad ,  Meng-Chang Lee ,  Dirk Leipold

IPC分类号： H04Q7/20 ,  H03M1/12 ,  H04B1/16

CPC分类号： H04B1/28 ,  H03M1/183 ,  H04B1/0007

摘要： Methods and apparatus to perform radio frequency (RF) analog-to-digital conversion are described. According to one example, a receiver includes an amplifier to amplify received analog RF signals and a mixer-free circuit for converting the received analog RF signals to digital signals.

摘要翻译： 描述了执行射频（RF）模数转换的方法和装置。 根据一个示例，接收机包括用于放大接收到的模拟RF信号的放大器和用于将所接收的模拟RF信号转换为数字信号的无混频器电路。

公开(公告)号：US20060290435A1

公开(公告)日：2006-12-28

申请号：US11464420

申请日：2006-08-14

申请人： Robert Staszewski ,  Dirk Leipold ,  Khurram Muhammad

发明人： Robert Staszewski ,  Dirk Leipold ,  Khurram Muhammad

IPC分类号： H03L7/00

CPC分类号： H03L7/1075 ,  H03F1/0211 ,  H03F1/3282 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L2207/50

摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.

摘要翻译： 用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。 优选实施例包括具有比例环路增益路径（比例环路增益电路1115）和积分环路增益模块（积分环路增益模块1120）的环路滤波器。 在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。 然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。 可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。

公开(公告)号：US07003276B2

公开(公告)日：2006-02-21

申请号：US10132025

申请日：2002-04-25

申请人： Khurram Muhammad ,  Dirk Leipold ,  Kenneth J. Maggio

发明人： Khurram Muhammad ,  Dirk Leipold ,  Kenneth J. Maggio

IPC分类号： H04B1/26

CPC分类号： H04B1/0025 ,  H03H15/00 ,  H03H19/004 ,  H04B1/0003 ,  H04B1/28 ,  H04L27/24

摘要： A first periodic voltage waveform (20) is downconverted into a second periodic voltage waveform (35, 36). A plurality of temporally distinct samples (SA1, SA2, . . . ) respectively indicative of areas under corresponding fractional-cycles of the first voltage waveform are obtained. The samples are combined to produce the second voltage waveform. The samples can be manipulated to provide gain adjustment to the second voltage waveform. The samples are obtained by charging a sampling capacitance in response to a current waveform that corresponds to the first voltage waveform. The use of different sampling capacitances during respective predetermined time intervals permits the signal strength of the first waveform to be determined from observation of the second waveform.

摘要翻译： 第一周期性电压波形（20）被下变频成第二周期性电压波形（35,36）。 获得分别表示第一电压波形的相应分数周期下的面积的多个时间上不同的样本（SA 1，SA 2 ...）。 将样品组合以产生第二电压波形。 可以操作样品以对第二电压波形提供增益调整。 通过响应于对应于第一电压波形的电流波形对采样电容进行充电来获得样本。 在各个预定时间间隔期间使用不同的采样电容允许通过观察第二波形来确定第一波形的信号强度。

公开(公告)号：US06963732B2

公开(公告)日：2005-11-08

申请号：US10132436

申请日：2002-04-25

申请人： Khurram Muhammad ,  Dirk Leipold

发明人： Khurram Muhammad ,  Dirk Leipold

IPC分类号： H03H15/00 ,  H03H19/00 ,  H04B1/28 ,  H04B1/707 ,  H04L27/24 ,  H04B1/00

CPC分类号： H03H15/00 ,  H03H19/004 ,  H04B1/0003 ,  H04B1/0025 ,  H04B1/28 ,  H04L27/24

摘要： A first periodic voltage waveform (20) is downconverted into a second periodic voltage waveform (35, 36). A plurality of temporally distinct samples (SA1, SA2, . . . ) respectively indicative of areas under corresponding fractional-cycles of the first voltage waveform are obtained. The samples are combined to produce the second voltage waveform, and are also manipulated to implement a filtering operation such that the second voltage waveform represents a downconverted, filtered version of the first voltage waveform. The second waveform is driven by an amplifier stage (25), and the second waveform can be advantageously constructed so as to permit the amplifier stage to perform internal resets, offset corrections and other ancillary amplifier stage adjustments without losing information in the first waveform.

摘要翻译： 第一周期性电压波形（20）被下变频成第二周期性电压波形（35,36）。 获得分别表示第一电压波形的相应分数周期下的面积的多个时间上不同的样本（SA 1，SA 2 ...）。 将样本组合以产生第二电压波形，并且还被操纵以实现滤波操作，使得第二电压波形表示第一电压波形的下变换的滤波版本。 第二波形由放大器级（25）驱动，并且第二波形可以有利地构造成允许放大器级执行内部复位，偏移校正和其它辅助放大器级调整，而不会丢失第一波形中的信息。

公开(公告)号：US20050212606A1

公开(公告)日：2005-09-29

申请号：US11122670

申请日：2005-05-04

申请人： Robert Staszewski ,  Dirk Leipold ,  Khurram Muhammad

发明人： Robert Staszewski ,  Dirk Leipold ,  Khurram Muhammad

IPC分类号： H03F1/02 ,  H03F1/32 ,  H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H03L7/00

CPC分类号： H03L7/1075 ,  H03F1/0211 ,  H03F1/3282 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L2207/50

摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a wireless communication device having a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.

摘要翻译： 用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。 优选实施例包括具有带有比例环路增益路径（比例环路增益电路1115）和积分环路增益块（积分环路增益块1120）的环路滤波器的无线通信设备。 在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。 然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。 可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。

公开(公告)号：US20050130618A1

公开(公告)日：2005-06-16

申请号：US11028995

申请日：2005-01-03

申请人： Robert Staszewski ,  Khurram Muhammad ,  Yo-Chuol Ho ,  Dirk Leipold

发明人： Robert Staszewski ,  Khurram Muhammad ,  Yo-Chuol Ho ,  Dirk Leipold

IPC分类号： H03D7/12 ,  H04B1/10 ,  H04B1/06 ,  H04B7/00 ,  H04L7/00

CPC分类号： H03D7/125 ,  H04B1/1036

摘要： A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having multiple clock generating hardware significantly increases power consumption and integrated circuit area when the mixer 1100 is integrated into silicon. A method and apparatus 1125 containing a circuit for generating a set of clock signals that can be shared by the different signal paths is presented. Advantage is taken of the significant capacitance difference between different sampling capacitors in the mixer and the superposition property.

摘要翻译： 具有多个信号路径的混频器1100通常需要用于每个信号路径的单独的时钟产生硬件。 然而，当混合器1100集成到硅中时，具有多个时钟产生硬件的冗余显着地增加了功耗和集成电路面积。 提出了一种包含用于生成可由不同信号路径共享的一组时钟信号的电路的方法和装置1125。 利用混频器中不同采样电容器之间的显着电容差和叠加特性。

公开(公告)号：US08411793B2

公开(公告)日：2013-04-02

申请号：US13081338

申请日：2011-04-06

申请人： Robert B. Staszewski ,  Sameh Rezeq ,  Dirk Leipold

发明人： Robert B. Staszewski ,  Sameh Rezeq ,  Dirk Leipold

IPC分类号： H04K1/02

CPC分类号： H04L27/361

摘要： A transmitter using quadrature modulation includes a rectangular to polar converter for converting data symbols into a polar form, where each polar symbol has a magnitude signal and an angle signal. Digital phase modulation circuitry includes an all digital PLL circuit for generating a phase modulated RF carrier signal responsive to the angle signal frequency control word (FCW) and a carrier frequency FCW. A digitally controlled amplifier for amplifying the phase modulated signal is controlled by a digital amplitude control circuitry for controlling the gain of the digitally controlled amplifier responsive to the magnitude signal.

摘要翻译： 使用正交调制的发射机包括用于将数据符号转换成极性形式的矩形到极化转换器，其中每个极性符号具有幅度信号和角度信号。 数字相位调制电路包括全数字PLL电路，用于响应角度信号频率控制字（FCW）和载波频率FCW产生相位调制的RF载波信号。 用于放大相位调制信号的数字控制放大器由数字幅度控制电路控制，用于响应于幅度信号来控制数字控制放大器的增益。

公开(公告)号：US07767995B2

公开(公告)日：2010-08-03

申请号：US11846993

申请日：2007-08-29

申请人： Robert B. Staszewski ,  Renaldi Winoto ,  Dirk Leipold

发明人： Robert B. Staszewski ,  Renaldi Winoto ,  Dirk Leipold

IPC分类号： H01L29/06

CPC分类号： H01L27/092 ,  H01L29/66151 ,  H01L29/88 ,  Y10S438/979 ,  Y10S977/937

摘要： A method of providing a p-type substrate, disposing a pad oxide layer on the p-type substrate, disposing a nitride layer on the pad oxide layer, forming a nitride window in the nitride layer, disposing a field oxide in the nitride window, disposing a polysilicon gate over the field oxide, and diffusing a n-doped region in the p-type substrate, thereby forming at least one single-electron tunnel junction between the polysilicon gate and the n-doped region.

摘要翻译： 一种提供p型衬底的方法，在p型衬底上设置焊盘氧化物层，在衬垫氧化物层上设置氮化物层，在氮化物层中形成氮化物窗，在氮化物窗中设置场氧化物， 在场氧化物上设置多晶硅栅极，并扩散p型衬底中的n掺杂区域，从而在多晶硅栅极和n掺杂区域之间形成至少一个单电子隧道结。

公开(公告)号：US07483508B2

公开(公告)日：2009-01-27

申请号：US10306655

申请日：2002-11-27

申请人： Robert B. Staszewski ,  Dirk Leipold

发明人： Robert B. Staszewski ,  Dirk Leipold

IPC分类号： H03D3/24

CPC分类号： H03L7/085 ,  H03L7/0991

摘要： An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (KDCO) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (Δfmax) in the oscillating frequency; (2) a portion (TUNE_TF) of the tuning word can be dithered (1202), and the resultant dithered portion (dkTF) can then be applied to a control input of switchable devices within the digitally controlled oscillator; and (3) a non-linear differential term (187, 331) can be used to expedite correction of the digitally controlled oscillator when large phase error changes (335) occur.

摘要翻译： 全数字频率合成器架构围绕数字控制振荡器（DCO）构建，该振荡器响应于数字调谐字（OTW）进行调谐。 在示例性实施例中：（1）数字控制振荡器的增益特性（KDCO）可以通过在振荡频率中的已知改变（Deltafmax）之前和之后观察数字控制字来确​​定; （2）可以对调谐字的一部分（TUNE_TF）进行抖动（1202），然后将所得到的抖动部分（dkTF）施加到数字控制振荡器内的可切换装置的控制输入端; 和（3）当大相位误差变化（335）发生时，可以使用非线性微分项（187,331）来加速数字控制振荡器的校正。