-
公开(公告)号：US11587619B2
公开(公告)日：2023-02-21
申请号：US17360677
申请日：2021-06-28
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Jiahui Yuan , Deepanshu Dutta
Abstract: A memory device is provided in which blocks of memory cells are divided into separate portions or sub-blocks with respective sets of word line switching transistors. The sub-blocks can be arranged on a substrate on opposite sides of a dividing line, where a separate set of bit lines is provided on each side of the dividing line. Each block has a row decoder which provides a common word line voltage signal to each sub-block of the block. However, each sub-block can have an independent set of word line switching transistors so that the common word line voltage signal can be passed or blocked independently for each sub-block. The blocks of memory cells can be provided on a first die which is inverted and bonded to a second die which includes the sets of word line switching transistors.
-
公开(公告)号：US20220319605A1
公开(公告)日：2022-10-06
申请号：US17218498
申请日：2021-03-31
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Hua-Ling Hsu , Huai-Yuan Tseng , Fanglin Zhang
Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and configured to retain a threshold voltage corresponding to one of a plurality of data states following a program operation. A control circuit is coupled to the word lines and the bit lines. The control circuit is configured to count a bit-scan quantity of the memory cells during a bit-scan of the program operation. The control circuit determines whether the bit-scan quantity of the plurality of memory cells is greater than at least one predetermined bit-scan threshold. In response to the bit-scan quantity of the memory cells being greater than the at least one predetermined bit-scan threshold, the control circuit is configured to adjust a word line ramp rate of a word line voltage applied to the word lines during the program operation.
-
公开(公告)号：US20220223214A1
公开(公告)日：2022-07-14
申请号：US17149136
申请日：2021-01-14
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Huai-yuan Tseng , Tomer Eliash
Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and arranged in a plurality of planes. The apparatus also includes a control circuit coupled to the word lines and the bit lines and configured to determine whether a program operation of the memory cells involves all of the plurality of planes. In response to the program operation of the memory cells not involving all of the plurality of planes, the control circuit adjusts at least one of a bit line ramp rate of a bit line voltage applied to the bit lines and a word line ramp rate of at least one word line voltage applied to the word lines during the program operation based on a quantity of the plurality of planes associated with the memory cells being program-verified in the program operation.
-
公开(公告)号：US11355208B2
公开(公告)日：2022-06-07
申请号：US16916790
申请日：2020-06-30
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Fanglin Zhang , Zhuojie Li , Huai-Yuan Tseng
IPC: G11C16/06 , G11C16/34 , G11C16/04 , G11C16/10 , H01L27/11582 , G11C16/26 , H01L27/11565 , G11C11/56
Abstract: Apparatus and methods are described to program memory cells and verify stored values programmed into the cells. The next stage in stored memory can be moved to the current verification iteration when certain conditions are met. Verification can include counting bits that exceed a voltage value for a stage being verified to produce a bit count number and determining if the bit count number for the stage being verified meets a threshold value. If the bit count number does not meet the threshold, the verification process can continue with a current verify iteration and thereafter move to a next verify iteration. If the bit count number does meet the threshold, the process can add a next stage to the current verify iteration and thereafter move to a next verify iteration.
-
公开(公告)号：US20210405891A1
公开(公告)日：2021-12-30
申请号：US16916620
申请日：2020-06-30
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Deepanshu Dutta , Huai-Yuan Tseng
IPC: G06F3/06
Abstract: An apparatus includes a controller and a plurality of memory dies operable connected to and controlled by the controller. Each of the memory dies draws a current from a current source during a program operation. The controller being configured to receive a clock signal from each of the memory dies; count the number of clock signal received to determine a count value; and dynamically stagger at least one of the memory dies relative to the other memory dies when the count value reaches a maximum count value within a threshold time. The controller operates to dynamically stagger operation of at least one memory die to prevent the group of memory dies from operating synchronously.
-
Patent Agency Ranking
公开(公告)号：US20210264964A1
公开(公告)日：2021-08-26
申请号：US16798718
申请日：2020-02-24
Applicant: SanDisk Technologies LLC
Inventor： Sarath Puthenthermadam , Yu-Chung Lien , Huai-Yuan Tseng
IPC: G11C11/4074 , G11C11/4094 , G11C11/408 , G11C7/14 , G11C5/02 , G11C5/14
Abstract: This disclosure relates to apparatuses and a method for retaining a bias in a NAND string channel during source-side precharge. The apparatuses include a memory array and a die controller configured to mitigate formation of a potential gradient in the channel of the memory array NAND strings during a program storage operation. To this end, a plurality of source-side select gates is activated, then each of the plurality of source side dummy word line select gates is activated. Next, a NAND string channel is biased by biasing the source line coupled to the NAND string by the plurality of source-side select gates. Finally, the plurality of source-side select gates and the plurality of source side dummy word line select gates are discharged such that the channel maintains an electrical path to the source line.
-
公开(公告)号：US20210241836A1
公开(公告)日：2021-08-05
申请号：US16778821
申请日：2020-01-31
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Huai-Yuan Tseng , Deepanshu Dutta
IPC: G11C16/26 , G11C5/06 , G11C16/10 , H01L27/11556 , H01L27/11582 , G11C5/02
Abstract: Techniques are described for optimizing the peak current during a program operation by controlling a timing and ramp rate of a program-inhibit voltage signal as a function of a program loop number and/or program progress. A transition voltage between a regulated ramp up rate and an unregulated ramp up rate can also be adjusted. For initial and final sets of program loops in a program operation, the ramp up of the program-inhibit voltage signal can occur early so that it overlaps with operations of sense circuits in updating their latches based on results from a verify test in a previous program loop. For an intermediate set of program loops, the overlap is avoided. The ramp up rate can be larger and the transition voltage smaller for the initial and final sets of program loops compared to the intermediate set of program loops.
-
公开(公告)号：US11037635B1
公开(公告)日：2021-06-15
申请号：US16784171
申请日：2020-02-06
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Tomer Eliash , Huai-Yuan Tseng
Abstract: Apparatuses and techniques are described for managing power consumption in a memory device. When a multi-plane read command is received, a control circuit determines whether the blocks identified by the read command are fully or partially programmed. If they are fully programmed, the read command is executed while applying a common read pass voltage to the unprogrammed word lines of the respective blocks. If the blocks are not all fully programmed, the control circuit determines a last-programmed word line. If the last-programmed word lines are not equal in each block, the read command is executed while applying a base read pass voltage to the unprogrammed word lines of one or more higher-programmed blocks and a lower read pass voltage to the unprogrammed word lines of one or more lower-programmed blocks.
-
公开(公告)号：US10861537B1
公开(公告)日：2020-12-08
申请号：US16668886
申请日：2019-10-30
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Huai-Yuan Tseng , Deepanshu Dutta , Abhijith Prakash
IPC: G11C11/56 , G11C11/4074 , G11C11/409 , G11C11/408
Abstract: Techniques are provided for operating non-volatile storage. Peak current consumption may be reduced in connection with sensing non-volatile memory cells. Peak current consumption may be reduced when a first read condition is present. In one aspect, the value of a parameter of a voltage that is applied to a word line during a pre-read phase of a sense operation is controlled in order to reduce peak current consumption when the first read condition is present. Examples of the parameter include a ramp rate, a number of intermediate voltage levels, and a start time.
-
公开(公告)号：US10541038B2
公开(公告)日：2020-01-21
申请号：US16205165
申请日：2018-11-29
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Xiang Yang , Zhenming Zhou , Deepanshu Dutta , Huai-Yuan Tseng
Abstract: An apparatus, system, and method are disclosed for identifying and selecting a subgroup of memory cells for use during a programming or erasing operation, in order to execute the programming or erasing operation in less time, while avoiding over and under programming errors. Memory devices disclosed herein may include a state change/programming circuit, a counting circuit, a determination circuit, an identification circuit, and/or a subgroup selection circuit, where each of these circuits are configured to perform operations related to the overall process of identifying and selecting the subgroup of memory cells for utilization during a programming operation.
-
-
-
-
-
-
-
-
-
Search Results
70
records
(took 0.024 seconds)
