公开(公告)号：US11287994B2

公开(公告)日：2022-03-29

申请号：US16746803

申请日：2020-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changho Choi ,  Timothy Bisson ,  Ke Chen

IPC: G06F3/06 ,  G06F15/173

Abstract: Inventive aspects include a method, apparatus, and system for supporting a native key-value distributed storage system. The system includes a namenode having a KV-SSD and one or more datanodes each including one or more KV-SSDs. The system includes a client device that is communicatively coupled to the namenode and the one or more datanodes. The client device includes a native key-value storage and networking stack. Some embodiments include a hybrid block-based native key-value distributed storage system that supports both block-based files and native key-value tuples.

公开(公告)号：US20210264298A1

公开(公告)日：2021-08-26

申请号：US16872194

申请日：2020-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nima Elyasi ,  Vikas Sinha ,  Qinling Zheng ,  Changho Choi

IPC: G06N5/04 ,  G06F16/23 ,  G06N20/00

Abstract: In a method for training a machine learning model, the method includes: segmenting, by a processor, a dataset from a database into one or more datasets based on time period windows; assigning, by the processor, one or more weighted values to the one or more datasets according to the time period windows of the one or more datasets; generating, by the processor, a training dataset from the one or more datasets according to the one or more weighted values; and training, by the processor, the machine learning model using the training dataset.

公开(公告)号：US20210255792A1

公开(公告)日：2021-08-19

申请号：US16795510

申请日：2020-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Oluwole Jaiyeoba ,  Nima Elyasi ,  Changho Choi

IPC: G06F3/06

Abstract: A system and method for processing unstructured source data is described. Input data having a range of V is loaded from off-chip storage to on-chip storage. The input data is partitioned into P temporary parent partitions via the on-chip storage, where a particular one of the P temporary parent partitions has a range of V/P. The P temporary parent partitions are stored from the on-chip storage to the off-chip storage. The P temporary parent partitions are partitioned for generating P temporary child partitions until the target number of T partitions is generated, where data from of the P temporary parent partitions is source data for recursively loading, partitioning, and storing the source data. An application is configured to access partitioned data from the T partitions for generating an output. The accesses of the partitioned data are sequential read accesses of the off-chip storage.

公开(公告)号：US10824576B2

公开(公告)日：2020-11-03

申请号：US16294751

申请日：2019-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Janki S. Bhimani ,  Jingpei Yang ,  Changho Choi ,  Jianjian Huo

IPC: G06F12/00 ,  G06F13/18 ,  G06N3/00 ,  G06F3/06 ,  G06F16/23 ,  G06F12/02 ,  G06N20/00

Abstract: A multi-streaming memory system includes a memory, and a processor coupled to the memory, the processor executing a software component that is configured to identify multiple attributes that are each related to logical block addresses (LBAs), and that each correspond to each of a plurality of streams of data writes, evaluate an importance factor for each of the attributes for each of the streams, and clustering two or more of the LBAs by assigning a stream ID to each of the LBAs based on all of the importance factors for each of the LBAs and the assigned stream.

公开(公告)号：US10684956B2

公开(公告)日：2020-06-16

申请号：US15949943

申请日：2018-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changho Choi ,  Nima Elyasi

IPC: G06F12/10 ,  G06F3/06

Abstract: A system and method for an LBA RAID storage device. The LBA RAID storage device includes a plurality of data channels and a plurality of storage components. Each of the storage components is connected to one of the plurality of data channels. A storage controller is configured to receive a data and write the data to a RAID group made up of at least two storage components of the plurality of storage components that are each connected to a separate data channel.

公开(公告)号：US20190250821A1

公开(公告)日：2019-08-15

申请号：US16397543

申请日：2019-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sushma Devendrappa ,  James Liu ,  Changho Choi ,  Xiling Sun

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/061 ,  G06F3/0616 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1036 ,  G06F2212/7205 ,  G06F2212/7211

Abstract: An electronic system includes: a key value storage device, configured to transfer user data, the key value storage device including: a non-volatile memory array accessed by a key value address, an interface circuit, coupled to the non-volatile memory array, configured to receive a key value transfer command, a volatile memory, coupled to the interface circuit and the non-volatile memory array, configured to reduce a number of copies of the user data in the non-volatile memory array, and a device processor, coupled to the interface circuit, configured to manage the non-volatile memory array, the volatile memory, and the interface circuit by a key value index tree, including a key value translation block, to access the user data.

公开(公告)号：US10255955B2

公开(公告)日：2019-04-09

申请号：US15097234

申请日：2016-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hingkwan Huen ,  Changho Choi

IPC: G06F12/12 ,  G11C7/10 ,  G06F3/06

Abstract: A multi-port memory device in communication with a controller includes a memory array for storing data provided by the controller, a first port coupled to the controller via a first controller channel, a second port coupled to the controller via a second controller channel, a processor, and a processor memory local to the processor, wherein the processor memory has stored thereon instructions that, when executed by the processor, cause the processor to: enable data transfer through the first port and/or the second port in response to a first control signal received from the first controller channel and/or a second control signal received from second controller channel, decode at least one of the received first and second control signals to identify a data operation to perform, the identified data operation including a read or write operation from or to the memory array, and execute the identified data operation.

公开(公告)号：US20170229159A1

公开(公告)日：2017-08-10

申请号：US15097234

申请日：2016-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hingkwan Huen ,  Changho Choi

IPC: G11C7/10 ,  G06F3/06

CPC classification number: G11C7/1075 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0685

Abstract: A multi-port memory device in communication with a controller includes a memory array for storing data provided by the controller, a first port coupled to the controller via a first controller channel, a second port coupled to the controller via a second controller channel, a processor, and a processor memory local to the processor, wherein the processor memory has stored thereon instructions that, when executed by the processor, cause the processor to: enable data transfer through the first port and/or the second port in response to a first control signal received from the first controller channel and/or a second control signal received from second controller channel, decode at least one of the received first and second control signals to identify a data operation to perform, the identified data operation including a read or write operation from or to the memory array, and execute the identified data operation.

公开(公告)号：US20160299688A1

公开(公告)日：2016-10-13

申请号：US14926674

申请日：2015-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sushma Devendrappa ,  James Liu ,  Changho Choi ,  Sun Xiling

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/061 ,  G06F3/0616 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1036 ,  G06F2212/7205 ,  G06F2212/7211

Abstract: An electronic system includes: a key value storage device, configured to transfer user data, including: a non-volatile memory array, an interface circuit, coupled to the non-volatile memory array, configured to receive a key value transfer command, a volatile memory, coupled to the interface circuit and the non-volatile memory array, configured to transfer the user data with the interface circuit or the non-volatile memory array, and a device processor, coupled to the interface circuit, configured to manage the non-volatile memory array, the volatile memory, and the interface circuit by a key value index tree to access the user data; and wherein: the interface circuit, connected to a device coupling structure, configured to receive the key value transfer command; and the device processor is configured to address the non-volatile memory array, the volatile memory, or both concurrently based on a key value transfer.

Abstract translation: 电子系统包括：键值存储装置，被配置为传送用户数据，包括：非易失性存储器阵列，耦合到所述非易失性存储器阵列的接口电路，被配置为接收键值传送命令，易失性 存储器，耦合到所述接口电路和所述非易失性存储器阵列，被配置为用所述接口电路或所述非易失性存储器阵列传送所述用户数据;以及设备处理器，其耦合到所述接口电路， 易失性存储器阵列，易失性存储器和接口电路由键值索引树访问用户数据; 并且其中：连接到设备耦合结构的接口电路被配置为接收键值传送命令; 并且设备处理器被配置为基于键值传送来同时寻址非易失性存储器阵列，易失性存储器或两者。

公开(公告)号：US12260347B2

公开(公告)日：2025-03-25

申请号：US18197717

申请日：2023-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Qinling Zheng ,  Nima Elyasi ,  Vikas Sinha ,  Changho Choi

IPC: G06N5/04 ,  G06F11/16 ,  G06N20/00

Abstract: A method for predicting a time-to-failure of a target storage device may include training a machine learning scheme with a time-series dataset, and applying the telemetry data from the target storage device to the machine learning scheme which may output a time-window based time-to-failure prediction. A method for training a machine learning scheme for predicting a time-to-failure of a storage device may include applying a data quality improvement framework to a time-series dataset of operational and failure data from multiple storage devices, and training the scheme with the pre-processed dataset. A method for training a machine learning scheme for predicting a time-to-failure of a storage device may include training the scheme with a first portion of a time-series dataset of operational and failure data from multiple storage devices, testing the machine learning scheme with a second portion of the time-series dataset, and evaluating the machine learning scheme.