公开(公告)号：US20200293191A1

公开(公告)日：2020-09-17

申请号：US16887341

申请日：2020-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sushma Devendrappa ,  James Liu ,  Changho Choi ,  Xiling Sun

IPC: G06F3/06 ,  G06F12/02

Abstract: An electronic system includes: a key value storage device, configured to transfer user data, the key value storage device including: a non-volatile memory array accessed by a key value address, an interface circuit, coupled to the non-volatile memory array, configured to receive a key value transfer command, a volatile memory, coupled to the interface circuit and the non-volatile memory array, configured to reduce a number of copies of the user data in the non-volatile memory array, and a device processor, coupled to the interface circuit, configured to manage the non-volatile memory array, the volatile memory, and the interface circuit by a key value index tree, including a key value translation block, to access the user data.

公开(公告)号：US09817586B2

公开(公告)日：2017-11-14

申请号：US15134361

申请日：2016-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Fei Liu ,  Yang Seok Ki ,  Xiling Sun

IPC: G06F3/00 ,  G06F13/00 ,  G06F3/06 ,  G06F13/26 ,  G06F13/22

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/067 ,  G06F13/22 ,  G06F13/26

Abstract: A system and method for enabling an application (125, 305, 310, 315) and a storage device (120) to be more aware of each other may include a computer (105), a processor (110), and a memory (115) as well as the storage device (120). An application (125, 305, 310, 315) stored in the memory may communicate with a user space device driver (130). The user space device driver (130) may include a Mode Configure Module (320) to receive an application profile (405, 430, 435) from the application (125, 305, 310, 315) and an Application Aware Module (325) to receive I/O commands (555) from the application (125, 305, 310, 315) and place them in command queues (510, 515, 520, 525, 535, 540, 545, 550) according to the application profile (405, 430, and 435). The I/O commands (555) may then be sent to the storage device (120).

公开(公告)号：US11630578B2

公开(公告)日：2023-04-18

申请号：US16887341

申请日：2020-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sushma Devendrappa ,  James Liu ,  Changho Choi ,  Xiling Sun

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06 ,  G06F12/02

Abstract: An electronic system includes: a key value storage device, configured to transfer user data, the key value storage device including: a non-volatile memory array accessed by a key value address, an interface circuit, coupled to the non-volatile memory array, configured to receive a key value transfer command, a volatile memory, coupled to the interface circuit and the non-volatile memory array, configured to reduce a number of copies of the user data in the non-volatile memory array, and a device processor, coupled to the interface circuit, configured to manage the non-volatile memory array, the volatile memory, and the interface circuit by a key value index tree, including a key value translation block, to access the user data.

公开(公告)号：US20190250821A1

公开(公告)日：2019-08-15

申请号：US16397543

申请日：2019-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sushma Devendrappa ,  James Liu ,  Changho Choi ,  Xiling Sun

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/061 ,  G06F3/0616 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1036 ,  G06F2212/7205 ,  G06F2212/7211

Abstract: An electronic system includes: a key value storage device, configured to transfer user data, the key value storage device including: a non-volatile memory array accessed by a key value address, an interface circuit, coupled to the non-volatile memory array, configured to receive a key value transfer command, a volatile memory, coupled to the interface circuit and the non-volatile memory array, configured to reduce a number of copies of the user data in the non-volatile memory array, and a device processor, coupled to the interface circuit, configured to manage the non-volatile memory array, the volatile memory, and the interface circuit by a key value index tree, including a key value translation block, to access the user data.

公开(公告)号：US10747443B2

公开(公告)日：2020-08-18

申请号：US16397543

申请日：2019-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sushma Devendrappa ,  James Liu ,  Changho Choi ,  Xiling Sun

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G06F3/06 ,  G06F12/02

Abstract: An electronic system includes: a key value storage device, configured to transfer user data, the key value storage device including: a non-volatile memory array accessed by a key value address, an interface circuit, coupled to the non-volatile memory array, configured to receive a key value transfer command, a volatile memory, coupled to the interface circuit and the non-volatile memory array, configured to reduce a number of copies of the user data in the non-volatile memory array, and a device processor, coupled to the interface circuit, configured to manage the non-volatile memory array, the volatile memory, and the interface circuit by a key value index tree, including a key value translation block, to access the user data.

公开(公告)号：US09965412B2

公开(公告)日：2018-05-08

申请号：US14970293

申请日：2015-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Fei Liu ,  Yang Seok Ki ,  Xiling Sun

IPC: G06F13/24 ,  G06F13/22 ,  G06F13/40

CPC classification number: G06F13/24 ,  G06F13/22 ,  G06F13/4022

Abstract: According to one embodiment, a computer system includes a host computer, and a storage device coupled to the host computer. The host computer has a user-space device driver of the storage device in a user space of a host operating system (OS). The user-space device driver is configured to handle I/O operations to and from the storage device based on an application running on the host computer.

公开(公告)号：US20170109080A1

公开(公告)日：2017-04-20

申请号：US15062855

申请日：2016-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Fei Liu ,  Yang Seok Ki ,  Xiling Sun

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F12/0842 ,  G06F12/109 ,  G06F2212/1048

Abstract: A computing system includes a memory module, including a memory bank and a memory rank; and a control unit, coupled to the memory module, configured to: determine a core memory affinity between an aggregated memory and a CPU core; designate the memory bank and the memory rank, from the aggregated memory, as a core affiliated memory for the CPU core based on the core memory affinity; and allocate a slab class from the core affiliated memory to an application program based on a core application affinity with the CPU core.