公开(公告)号：US20200013784A1

公开(公告)日：2020-01-09

申请号：US16454532

申请日：2019-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： GUK IL AN ,  Keun Hwi Cho ,  Sung Min Kim ,  Yoon Moon Park

IPC: H01L27/1159 ,  H01L27/11592

Abstract: A semiconductor device includes: a substrate including a first region and a second region; a first interfacial layer disposed on the substrate in the first region and having a first thickness; a second interfacial layer disposed on the substrate in the second region, wherein the second interfacial layer includes a second thickness that is smaller than the first thickness; a first gate insulating layer disposed on the first interfacial layer and including a first ferroelectric material layer; a second gate insulating layer disposed on the second interfacial layer; a first gate electrode disposed on the first gate insulating layer; and a second gate electrode disposed on the second gate insulating layer.

公开(公告)号：US10529712B2

公开(公告)日：2020-01-07

申请号：US15971483

申请日：2018-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Min Kim ,  Dong Won Kim

IPC: H01L29/06 ,  H01L27/088 ,  H01L23/528 ,  H01L27/02 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/417 ,  H01L21/762 ,  H01L23/485 ,  H01L21/02 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311

Abstract: A semiconductor device includes a substrate, a fin structure protruding from the substrate in a direction perpendicular to an upper surface of the substrate, the fin structure including first fin regions extending in a first direction and second fin regions extending in a second direction different from the first direction, source/drain regions disposed on the fin structure, a gate structure intersecting the fin structure, a first contact connected to one of the source/drain regions, and a second contact connected to the gate structure and being between the second fin regions in plan view.

公开(公告)号：US10453839B2

公开(公告)日：2019-10-22

申请号：US16258833

申请日：2019-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Min Kim ,  Dong Won Kim ,  Geum Jong Bae

IPC: H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a plurality of fins comprising a first fin, a second fin, a third fin, a fourth fin and a fifth fin, each of the plurality of protruding from the substrate in a first direction, and spaced apart from one another in a second direction that intersects the first direction and a plurality of trenches comprising a first trench, a second trench, a third trench and a fourth trench, each of the plurality of trenches being formed between adjacent fins of the plurality of fins, wherein variation of a first width of the first trench and a third width of the third trench is smaller than a first variation, wherein variation of a second width of the second trench and a fourth width of the fourth trench is smaller than a second variation, and wherein the second variation is greater than the first variation.

公开(公告)号：US10229908B2

公开(公告)日：2019-03-12

申请号：US15709023

申请日：2017-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Min Kim ,  Dong Won Kim ,  Geum Jong Bae

IPC: H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a plurality of fins comprising a first fin, a second fin, a third fin, a fourth fin and a fifth fin, each of the plurality of protruding from the substrate in a first direction, and spaced apart from one another in a second direction that intersects the first direction and a plurality of trenches comprising a first trench, a second trench, a third trench and a fourth trench, each of the plurality of trenches being formed between adjacent fins of the plurality of fins, wherein variation of a first width of the first trench and a third width of the third trench is smaller than a first variation, wherein variation of a second width of the second trench and a fourth width of the fourth trench is smaller than a second variation, and wherein the second variation is greater than the first variation.

公开(公告)号：US20170365505A1

公开(公告)日：2017-12-21

申请号：US15343151

申请日：2016-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Kyungseok Oh ,  Sung Min Kim

IPC: H01L21/762 ,  H01L21/324 ,  H01L21/306

CPC classification number: H01L21/76205 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76224

Abstract: A method of filling cavities in a semiconductor structure during fabrication. A layer of a first material, e.g., a polysilazane, is deposited on the semiconductor, and subjected to a first thermal process to change its chemical composition, e.g., to change it to silicon dioxide. It is then etched back, and the cycle of deposition, and thermal processing is repeated. The etch-back may also be repeated in one or more of the cycles after the first cycle, and a second thermal process, that may increase the density of one or more of the deposited layers, may be performed in one or more of the cycles.