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    Bi-directional weight cell
    1.
    发明授权
    Bi-directional weight cell 有权

    公开(公告)号：US10739186B2

    公开(公告)日：2020-08-11

    申请号：US15886753

    申请日：2018-02-01

    申请人： Samsung Electronics Co., Ltd.

    发明人： Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Titash Rakshit

    IPC分类号： G11C7/10 ,  G11C13/00 ,  G01G23/38 ,  G06G7/16 ,  G11C11/54 ,  G06N3/063 ,  G11C11/16

    摘要： A weight cell including first and second bi-directional memory elements each configured to switch between a first resistance state and a second resistance state different than the first resistance state. A first input line is connected to a first terminal of the first bi-directional memory element, and a second input line is connected to the first terminal of the second bi-directional memory element. A first diode in forward bias connects the second terminal of the first bi-directional memory element to a first output line, a second diode in reverse bias connects the second terminal of the second bi-directional memory element to a second output line, a third diode in reverse bias connects the second terminal of the first bi-directional memory element to the second output line, and a fourth diode in forward bias connects the second terminal of the second bi-directional memory element to the first output line.

    MEMORY DEVICE WITH STRONG POLARIZATION COUPLING
    3.
    发明申请
    MEMORY DEVICE WITH STRONG POLARIZATION COUPLING 审中-公开

    公开(公告)号：US20190318774A1

    公开(公告)日：2019-10-17

    申请号：US16142944

    申请日：2018-09-26

    申请人： Samsung Electronics Co., LTD.

    发明人： Jorge A. Kittl ,  Borna J. Obradovic ,  Ryan M. Hatcher ,  Titash Rakshit

    IPC分类号： G11C11/22

    摘要： A semiconductor memory device and method for providing the semiconductor memory device are described. The semiconductor memory device includes a ferroelectric capacitor. The ferroelectric capacitor includes a first electrode, a second electrode and a multilayer insulator structure between the first and second electrodes. The multilayer insulator structure includes at least one ferroelectric layer and at least one dielectric layer. The at least one ferroelectric layer and the at least one dielectric layer share at least one interface and have a strong polarization coupling.

    Filling processes
    5.
    发明授权
    Filling processes 有权

    公开(公告)号：US09847245B1

    公开(公告)日：2017-12-19

    申请号：US15343151

    申请日：2016-11-03

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jorge A. Kittl ,  Kyungseok Oh ,  Sung Min Kim

    IPC分类号： H01L21/762 ,  H01L21/306 ,  H01L21/324

    CPC分类号： H01L21/76205 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76224

    摘要： A method of filling cavities in a semiconductor structure during fabrication. A layer of a first material, e.g., a polysilazane, is deposited on the semiconductor, and subjected to a first thermal process to change its chemical composition, e.g., to change it to silicon dioxide. It is then etched back, and the cycle of deposition, and thermal processing is repeated. The etch-back may also be repeated in one or more of the cycles after the first cycle, and a second thermal process, that may increase the density of one or more of the deposited layers, may be performed in one or more of the cycles.

    Methods of forming a semiconductor layer including germanium with low defectivity
    6.
    发明授权
    Methods of forming a semiconductor layer including germanium with low defectivity 有权
    形成低缺陷锗的半导体层的方法

    公开(公告)号：US09406508B2

    公开(公告)日：2016-08-02

    申请号：US14480869

    申请日：2014-09-09

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jorge A. Kittl ,  Mark S. Rodder

    IPC分类号： H01L21/02 ,  H01L21/20

    CPC分类号： H01L21/02664 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02532

    摘要： Methods of forming a semiconductor layer including germanium with low defectivity are provided. The methods may include sequentially forming a silicate glass layer, a diffusion barrier layer including nitride and an interfacial layer including oxide on a substrate. The methods may also include forming a first semiconductor layer on the interfacial layer and converting a portion of the first semiconductor layer into a second semiconductor layer having a germanium concentration therein that is higher than a germanium concentration of the first semiconductor layer.

    摘要翻译： 提供了形成具有低缺陷度的锗的半导体层的方法。 所述方法可以包括依次形成硅酸盐玻璃层，包含氮化物的扩散阻挡层和在衬底上包含氧化物的界面层。 所述方法还可以包括在界面层上形成第一半导体层，并将第一半导体层的一部分转换成其锗浓度高于第一半导体层的锗浓度的第二半导体层。

    CONFINED SEMI-METAL FIELD EFFECT TRANSISTOR
    7.
    发明申请
    CONFINED SEMI-METAL FIELD EFFECT TRANSISTOR 有权
    限制半金属场效应晶体管

    公开(公告)号：US20160071970A1

    公开(公告)日：2016-03-10

    申请号：US14625376

    申请日：2015-02-18

    申请人： Samsung Electronics Co., Ltd.

    发明人： Ryan M. Hatcher ,  Jorge A. Kittl ,  Robert C. Bowen

    IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/66

    CPC分类号： H01L29/78 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/36 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/775

    摘要： Exemplary embodiments are disclosed for a semi-metal transistor, comprising: a semi-metal contact region adjacent to a metal contact; at least one semiconductor terminal; and a semi-metal transition region connected between the contact region and the semiconductor terminal that transitions from a substantially zero gap semi-metal beginning at an interface of the contact region into a semiconductor with an energy band gap towards the semiconductor terminal.

    摘要翻译： 公开了用于半金属晶体管的示例性实施例，包括：与金属接触相邻的半金属接触区域; 至少一个半导体端子; 以及连接在所述接触区域和所述半导体端子之间的半金属过渡区域，所述半金属过渡区域从从所述接触区域的界面开始的半金属基本上为零的间隙向具有朝向所述半导体端子的能带隙的半导体转变。

    INTERFACE LAYER FOR GATE STACK USING 03 POST TREATMENT
    8.
    发明申请
    INTERFACE LAYER FOR GATE STACK USING 03 POST TREATMENT 有权
    接口层使用03后处理

    公开(公告)号：US20160042956A1

    公开(公告)日：2016-02-11

    申请号：US14666770

    申请日：2015-03-24

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jorge A. Kittl ,  Mark S. Rodder ,  Wei-E Wang

    IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L29/778

    CPC分类号： H01L29/513 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/778

    摘要： Exemplary embodiments provide for fabricating a field effect transistor (FET) with an interface layer for a gate stack using an O3 post treatment. Aspects of the exemplary embodiments include: forming a semiconductor body upon a substrate; cleaning the surface of the semiconductor body; depositing a first dielectric layer on the semiconductor body; performing an O3 treatment that mixes with and penetrates the first dielectric layer and reacts with the semiconductor body to form a new interface layer; and performing gate stack processing, including deposition of a gate electrode.

    摘要翻译： 示例性实施例提供使用O3后处理来制造具有用于栅极堆叠的界面层的场效应晶体管（FET）。 示例性实施例的方面包括：在衬底上形成半导体本体; 清洁半导体体的表面; 在所述半导体主体上沉积第一电介质层; 执行与第一电介质层混合并渗透第一电介质层并与半导体本体反应以形成新界面层的O3处理; 以及执行栅堆叠处理，包括沉积栅电极。