公开(公告)号：US08779797B2

公开(公告)日：2014-07-15

申请号：US13544548

申请日：2012-07-09

Applicant: Sang Jin Byeon ,  Jae Jin Lee

Inventor： Sang Jin Byeon ,  Jae Jin Lee

IPC: H03K19/173

CPC classification number: H03K19/173

Abstract: A semiconductor apparatus has a plurality of chips stacked therein, and generation timing of read control signals for controlling read operations of the plurality of stacked chips is controlled such that times after a read command is applied to when data are outputted from respective chips are made to substantially correspond to one another.

Abstract translation: 半导体装置具有堆叠的多个芯片，并且控制用于控制多个堆叠芯片的读取操作的读取控制信号的生成定时，使得在将读取命令应用于从各个芯片输出数据之后的时间被制成 基本相对应。

公开(公告)号：US20120154008A1

公开(公告)日：2012-06-21

申请号：US13162702

申请日：2011-06-17

Applicant: Dae Suk KIM ,  Jong Chern Lee ,  Sang Jin Byeon

Inventor： Dae Suk KIM ,  Jong Chern Lee ,  Sang Jin Byeon

IPC: H03K3/289

CPC classification number: G06F13/4247

Abstract: A semiconductor apparatus may include a master chip, first to nth slave chips, first to nth slave chip ID generating units, and a master chip ID generating unit. The first to nth slave chip ID generating units are disposed respectively in the first to nth slave chips and connected in series to each other. Each of the first to nth slave chip ID generating units is configured to add a predetermined code value to an mth operation code to generate an (m+1)th operation code. The master chip ID generating unit is disposed in the master chip to generate a variable first operation code in response to a select signal. Here, ‘n’ is an integer that is equal to or greater than 2, and ‘m’ is an integer that is equal to or greater than 1 and equal to or smaller than ‘n’.

Abstract translation: 半导体装置可以包括主芯片，第一至第n从属芯片，第一至第n从属芯片ID生成单元和主芯片ID生成单元。 第1〜第n从属芯片ID生成部分分别配置在第1至第n从属芯片中并串联连接。 第一至第n从属芯片ID生成单元中的每一个被配置为向第m个操作码添加预定代码值，以生成第（m + 1）个操作代码。 主芯片ID产生单元设置在主芯片中，以响应于选择信号产生可变的第一操作码。 这里，'n'为2以上的整数，'m'为1以上且等于或小于'n'的整数。

公开(公告)号：US08081012B2

公开(公告)日：2011-12-20

申请号：US12649125

申请日：2009-12-29

Applicant: Sang Jin Byeon

Inventor： Sang Jin Byeon

IPC: H03K19/094

CPC classification number: H03K19/018528 ,  H03K19/00369

Abstract: A semiconductor buffer circuit that operates stably against PVT fluctuation is disclosed. The disclosed semiconductor buffer unit of the present invention includes: a detecting block configured to generate a plurality of code signals by detecting an external voltage, using a plurality of reference voltages; and a buffer unit configured to receive an input signal and the plurality of code signals and, based on the code signals, to generate an output signal, wherein a consumption of a driving current of the buffer unit is controlled based on the code signals.

Abstract translation: 公开了一种对PVT波动稳定运行的半导体缓冲电路。 本发明公开的半导体缓冲单元包括：检测块，被配置为使用多个参考电压通过检测外部电压来产生多个代码信号; 以及缓冲单元，被配置为接收输入信号和所述多个代码信号，并且基于所述代码信号来产生输出信号，其中基于所述代码信号来控制所述缓冲单元的驱动电流的消耗。

公开(公告)号：US20110187408A1

公开(公告)日：2011-08-04

申请号：US12836546

申请日：2010-07-14

Applicant: Sang Jin Byeon ,  Jae Jin Lee

Inventor： Sang Jin Byeon ,  Jae Jin Lee

IPC: H03K19/173

CPC classification number: H03K19/173

Abstract: A semiconductor apparatus has a plurality of chips stacked therein, and generation timing of read control signals for controlling read operations of the plurality of stacked chips is controlled such that times after a read command is applied to when data are outputted from respective chips are made to substantially correspond to one another.

Abstract translation: 半导体装置具有堆叠的多个芯片，并且控制用于控制多个堆叠芯片的读取操作的读取控制信号的生成定时，使得在将读取命令应用于从各个芯片输出数据之后的时间被制成 基本相对应。

公开(公告)号：US20110102006A1

公开(公告)日：2011-05-05

申请号：US12651066

申请日：2009-12-31

Applicant: Min Seok CHOI ,  Jong Chern LEE ,  Sang Jin Byeon ,  Young Jun KU

Inventor： Min Seok CHOI ,  Jong Chern LEE ,  Sang Jin Byeon ,  Young Jun KU

IPC: G01R31/26 ,  G01R31/3187

CPC classification number: G01R31/318513

Abstract: A circuit for testing a semiconductor apparatus includes a test voltage applying unit configured to apply a test voltage to a first end of a through-silicon via (TSV) in response to a test mode signal and a detecting unit configured to be connected to a second end of the TSV and detect a current outputted from the second end of the TSV.

Abstract translation: 一种用于测试半导体装置的电路包括：测试电压施加单元，被配置为响应于测试模式信号将测试电压施加到穿硅通孔（TSV）的第一端;以及检测单元，被配置为连接到第二 结束TSV，并检测从TSV的第二端输出的电流。

公开(公告)号：US07778100B2

公开(公告)日：2010-08-17

申请号：US12272944

申请日：2008-11-18

Applicant: Sang Jin Byeon

Inventor： Sang Jin Byeon

IPC: G11C5/14

CPC classification number: G11C5/14

Abstract: An internal voltage generation circuit of a semiconductor memory device controls a dead zone voltage, in which the driving unit that supplies a power supply voltage, does not need to operate. An internal voltage having a dead zone is determined by first and second driving signals based on a level of a reference voltage, and by selectively supplying first and second voltages by means of the first and second driving signals.

Abstract translation: 半导体存储器件的内部电压产生电路控制提供电源电压的驱动单元不需要操作的死区电压。 具有死区的内部电压基于参考电压的电平由第一和第二驱动信号确定，并且通过第一和第二驱动信号选择性地提供第一和第二电压。