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    Semiconductor apparatus and method for controlling the same
    2.
    发明授权
    Semiconductor apparatus and method for controlling the same 有权
    半导体装置及其控制方法

    公开(公告)号：US08766678B2

    公开(公告)日：2014-07-01

    申请号：US13584473

    申请日：2012-08-13

    申请人： Sin Hyun Jin ,  Sang Jin Byeon

    发明人： Sin Hyun Jin ,  Sang Jin Byeon

    IPC分类号： H03L7/00

    CPC分类号： H03K17/22 ,  H01L25/065 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element.

    摘要翻译： 半导体装置包括被配置为产生上电信号的上电信号生成部，被配置为驱动和输出上电信号的驱动器，以及主电路块，被配置为响应于来自所述上电信号的输出执行预定功能 驱动器，其中所述加电信号产生部分和所述驱动器的输入端子通过可断开元件连接。

    Apparatus and method for generating resistance calibration code in semiconductor integrated circuit
    3.
    发明授权
    Apparatus and method for generating resistance calibration code in semiconductor integrated circuit 有权
    在半导体集成电路中产生电阻校准码的装置和方法

    公开(公告)号：US08169232B2

    公开(公告)日：2012-05-01

    申请号：US12478201

    申请日：2009-06-04

    申请人： Sang Jin Byeon

    发明人： Sang Jin Byeon

    IPC分类号： H03K17/16 ,  H03K19/003 ,  H03K19/094 ,  H03K3/00 ,  H03B1/00

    CPC分类号： H03K19/00

    摘要： A resistance calibration code generating apparatus includes a code calibration unit configured to calibrate and output code values of a resistance calibration code during predetermined cycles of a calibration clock, which are determined by a code calibration time control command, and a calibration clock generating unit configured to output the calibration clock using a code calibration command.

    摘要翻译： 一种电阻校准代码生成装置，包括：代码校准单元，被配置为在通过代码校准时间控制命令确定的校准时钟的预定周期期间校准并输出电阻校准代码的代码值;以及校准时钟生成单元， 使用代码校准命令输出校准时钟。

    Internal voltage generation circuit of semiconductor memory device
    5.
    发明授权
    Internal voltage generation circuit of semiconductor memory device 有权
    半导体存储器件的内部电压产生电路

    公开(公告)号：US07468928B2

    公开(公告)日：2008-12-23

    申请号：US11648283

    申请日：2006-12-29

    申请人： Sang Jin Byeon

    发明人： Sang Jin Byeon

    IPC分类号： G11C5/14

    CPC分类号： G11C5/14

    摘要： An internal voltage generation circuit of a semiconductor memory device controls a dead zone voltage, in which the driving unit that supplies a power supply voltage, does not need to operate. An internal voltage having a dead zone is determined by first and second driving signals based on a level of a reference voltage, and by selectively supplying first and second voltages by means of the first and second driving signals.

    摘要翻译： 半导体存储器件的内部电压产生电路控制提供电源电压的驱动单元不需要操作的死区电压。 具有死区的内部电压基于参考电压的电平由第一和第二驱动信号确定，并且通过第一和第二驱动信号选择性地提供第一和第二电压。

    APPARATUS FOR SUPPLYING OVERDRIVING SIGNAL
    6.
    发明申请
    APPARATUS FOR SUPPLYING OVERDRIVING SIGNAL 失效
    供应信号传递装置

    公开(公告)号：US20080191748A1

    公开(公告)日：2008-08-14

    申请号：US11958277

    申请日：2007-12-17

    申请人： Sang Jin Byeon

    发明人： Sang Jin Byeon

    IPC分类号： H03K5/125

    CPC分类号： G11C7/08 ,  G11C5/143 ,  G11C5/145 ,  G11C11/4091

    摘要： An apparatus for supplying an overdriving signal in a memory apparatus. The apparatus includes: a voltage detecting block that outputs a plurality of detection signals according to the level of an external voltage, and a pulse generator that outputs the overdriving signals having different pulse widths according to the plurality of detection signals.

    摘要翻译： 一种用于在存储装置中提供过驱动信号的装置。 该装置包括：电压检测块，其根据外部电压的电平输出多个检测信号;以及脉冲发生器，其根据多个检测信号输出具有不同脉冲宽度的过驱动信号。

    Semiconductor memory device
    7.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07193920B2

    公开(公告)日：2007-03-20

    申请号：US11169949

    申请日：2005-06-30

    申请人： Sang Jin Byeon ,  Kee Teok Park

    发明人： Sang Jin Byeon ,  Kee Teok Park

    IPC分类号： G11C5/14

    CPC分类号： G11C5/14

    摘要： A semiconductor memory device generates a control signal for regulating a potential of an internal power voltage when an extended mode register is set to adjust an operating speed and a tWR (time to write recovery) of a chip. The semiconductor memory device comprises an extended mode register setting unit and an internal power voltage generating unit. When an internal circuit enters into a specific mode for high-speed operation, the extended mode register setting unit outputs a plurality of internal power control signals to regulate a potential of an internal power voltage of the internal circuit. The internal power voltage generating unit generates an internal power voltage by regulating the potential of the internal power voltage in response to the plurality of internal power control signals.

    摘要翻译： 当扩展模式寄存器被设置以调整芯片的操作速度和tWR（写入恢复时间）时，半导体存储器件产生用于调节内部电源电压的电位的控制信号。 半导体存储器件包括扩展模式寄存器设置单元和内部电源电压产生单元。 当内部电路进入用于高速运行的特定模式时，扩展模式寄存器设置单元输出多个内部功率控制信号以调节内部电路的内部电源电压的电位。 内部电力电压产生单元通过响应于多个内部功率控制信号调节内部电力电压的电位而产生内部电力电压。

    Semiconductor apparatus
    8.
    发明授权
    Semiconductor apparatus 有权
    半导体装置

    公开(公告)号：US08713349B2

    公开(公告)日：2014-04-29

    申请号：US13166094

    申请日：2011-06-22

    申请人： Sang Jin Byeon ,  Jae Bum Ko

    发明人： Sang Jin Byeon ,  Jae Bum Ko

    IPC分类号： G11C5/06

    CPC分类号： G11C5/04 ,  G11C16/20 ,  G11C2029/4402 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2924/00014

    摘要： A semiconductor apparatus may comprise: a first chip ID generation unit configured to receive an enable signal through a first through-silicon via and a clock signal through a second through-silicon via and generate a first chip ID signal and a delayed enable signal; a second chip ID generation unit configured to receive the delayed enable signal through a third through-silicon via from the first chip ID generation unit and the clock signal and generate a second chip ID signal; a first chip selection signal generation unit configured to receive the first chip ID signal and a main ID signal and generate a first chip selection signal; and a second chip selection signal generation unit configured to receive the second chip ID signal and the main ID signal and generate a second chip selection signal.

    摘要翻译： 半导体装置可以包括：第一芯片ID生成单元，被配置为通过第一穿通硅通孔接收使能信号和通过第二通过硅通孔的时钟信号，并生成第一芯片ID信号和延迟使能信号; 第二芯片ID生成单元，被配置为通过来自第一芯片ID生成单元的第三通过硅通孔和时钟信号接收延迟使能信号，并生成第二芯片ID信号; 第一芯片选择信号生成单元，被配置为接收第一芯片ID信号和主ID信号，并生成第一芯片选择信号; 以及第二芯片选择信号生成单元，被配置为接收第二芯片ID信号和主ID信号，并生成第二芯片选择信号。

    Semiconductor apparatus and data transmission method thereof
    9.
    发明授权
    Semiconductor apparatus and data transmission method thereof 有权
    半导体装置及其数据传输方法

    公开(公告)号：US08699280B2

    公开(公告)日：2014-04-15

    申请号：US13339062

    申请日：2011-12-28

    申请人： Sang Jin Byeon

    发明人： Sang Jin Byeon

    IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C8/00

    CPC分类号： G11C5/063 ,  G11C7/1048 ,  G11C7/1069

    摘要： A semiconductor apparatus includes a normal data line, an auxiliary data line and a data line selection unit. The normal data line is connected with a data selection unit. The auxiliary data line is connected with the data selection unit. The data line selection unit outputs data to one of the normal data line and the auxiliary data line in response to a command signal.

    摘要翻译： 半导体装置包括正常数据线，辅助数据线和数据线选择单元。 正常数据线与数据选择单元连接。 辅助数据线与数据选择单元连接。 数据线选择单元响应于命令信号将数据输出到正常数据线和辅助数据线之一。