公开(公告)号：US08369122B2

公开(公告)日：2013-02-05

申请号：US12838332

申请日：2010-07-16

Applicant: Sang Jin Byeon ,  Jae Jin Lee

Inventor： Sang Jin Byeon ,  Jae Jin Lee

IPC: G11C5/00 ,  G11C5/02 ,  G11C5/06 ,  G11C7/00 ,  G11C8/00

CPC classification number: H03L7/00

Abstract: A semiconductor apparatus has a plurality of chips stacked therein. Read control signals for controlling read operations of the plurality of chips are synchronized with a reference clock such that the time taken from the application of a read command to the output of data for each of the plurality of chips is maintained substantially the same.

Abstract translation: 半导体装置具有堆叠在其中的多个芯片。 用于控制多个芯片的读取操作的读取控制信号与参考时钟同步，使得从应用读取命令到多个芯片中的每一个的数据输出所花费的时间保持基本相同。

公开(公告)号：US08779797B2

公开(公告)日：2014-07-15

申请号：US13544548

申请日：2012-07-09

Applicant: Sang Jin Byeon ,  Jae Jin Lee

Inventor： Sang Jin Byeon ,  Jae Jin Lee

IPC: H03K19/173

CPC classification number: H03K19/173

Abstract: A semiconductor apparatus has a plurality of chips stacked therein, and generation timing of read control signals for controlling read operations of the plurality of stacked chips is controlled such that times after a read command is applied to when data are outputted from respective chips are made to substantially correspond to one another.

Abstract translation: 半导体装置具有堆叠的多个芯片，并且控制用于控制多个堆叠芯片的读取操作的读取控制信号的生成定时，使得在将读取命令应用于从各个芯片输出数据之后的时间被制成 基本相对应。

公开(公告)号：US20110187408A1

公开(公告)日：2011-08-04

申请号：US12836546

申请日：2010-07-14

Applicant: Sang Jin Byeon ,  Jae Jin Lee

Inventor： Sang Jin Byeon ,  Jae Jin Lee

IPC: H03K19/173

CPC classification number: H03K19/173

Abstract: A semiconductor apparatus has a plurality of chips stacked therein, and generation timing of read control signals for controlling read operations of the plurality of stacked chips is controlled such that times after a read command is applied to when data are outputted from respective chips are made to substantially correspond to one another.

Abstract translation: 半导体装置具有堆叠的多个芯片，并且控制用于控制多个堆叠芯片的读取操作的读取控制信号的生成定时，使得在将读取命令应用于从各个芯片输出数据之后的时间被制成 基本相对应。

公开(公告)号：US09030224B2

公开(公告)日：2015-05-12

申请号：US13339121

申请日：2011-12-28

Applicant: Jae Bum Ko ,  Sang Jin Byeon

Inventor： Jae Bum Ko ,  Sang Jin Byeon

IPC: G01R31/02 ,  G06F1/32 ,  G01R31/3185 ,  G11C5/14 ,  G11C29/02

CPC classification number: G06F1/32 ,  G01R31/318558 ,  G11C5/14 ,  G11C29/021

Abstract: A semiconductor integrated circuit includes a plurality of dies, wherein each of the dies is configured to enable a power circuit provided therein according to a power control signal, in a state in which the die was determined to be a good die or a fail die.

Abstract translation: 半导体集成电路包括多个管芯，其中，所述管芯中的每一个被配置为在所述管芯被确定为良好管芯或者失效管芯的状态下根据功率控制信号使能设置在其中的电源电路。

公开(公告)号：US08766678B2

公开(公告)日：2014-07-01

申请号：US13584473

申请日：2012-08-13

Applicant: Sin Hyun Jin ,  Sang Jin Byeon

Inventor： Sin Hyun Jin ,  Sang Jin Byeon

IPC: H03L7/00

CPC classification number: H03K17/22 ,  H01L25/065 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element.

Abstract translation: 半导体装置包括被配置为产生上电信号的上电信号生成部，被配置为驱动和输出上电信号的驱动器，以及主电路块，被配置为响应于来自所述上电信号的输出执行预定功能 驱动器，其中所述加电信号产生部分和所述驱动器的输入端子通过可断开元件连接。

公开(公告)号：US08169232B2

公开(公告)日：2012-05-01

申请号：US12478201

申请日：2009-06-04

Applicant: Sang Jin Byeon

Inventor： Sang Jin Byeon

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/094 ,  H03K3/00 ,  H03B1/00

CPC classification number: H03K19/00

Abstract: A resistance calibration code generating apparatus includes a code calibration unit configured to calibrate and output code values of a resistance calibration code during predetermined cycles of a calibration clock, which are determined by a code calibration time control command, and a calibration clock generating unit configured to output the calibration clock using a code calibration command.

Abstract translation: 一种电阻校准代码生成装置，包括：代码校准单元，被配置为在通过代码校准时间控制命令确定的校准时钟的预定周期期间校准并输出电阻校准代码的代码值;以及校准时钟生成单元， 使用代码校准命令输出校准时钟。

公开(公告)号：US20110109382A1

公开(公告)日：2011-05-12

申请号：US12650648

申请日：2009-12-31

Applicant: Sin Hyun JIN ,  Sang Jin Byeon

Inventor： Sin Hyun JIN ,  Sang Jin Byeon

IPC: H01L25/00

CPC classification number: G11C5/063 ,  G11C5/04 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16 ,  H01L2225/06527 ,  H01L2225/06541

Abstract: A semiconductor apparatus having a plurality of semiconductor chips is configured in such a manner that the plurality of semiconductor chips share one or more source voltages generated in one of the plurality of semiconductor chips.

Abstract translation: 具有多个半导体芯片的半导体装置被配置为使得多个半导体芯片共享在多个半导体芯片中的一个半导体芯片中生成的一个或多个源极电压。

公开(公告)号：US07468928B2

公开(公告)日：2008-12-23

申请号：US11648283

申请日：2006-12-29

Applicant: Sang Jin Byeon

Inventor： Sang Jin Byeon

IPC: G11C5/14

CPC classification number: G11C5/14

Abstract: An internal voltage generation circuit of a semiconductor memory device controls a dead zone voltage, in which the driving unit that supplies a power supply voltage, does not need to operate. An internal voltage having a dead zone is determined by first and second driving signals based on a level of a reference voltage, and by selectively supplying first and second voltages by means of the first and second driving signals.

Abstract translation: 半导体存储器件的内部电压产生电路控制提供电源电压的驱动单元不需要操作的死区电压。 具有死区的内部电压基于参考电压的电平由第一和第二驱动信号确定，并且通过第一和第二驱动信号选择性地提供第一和第二电压。

公开(公告)号：US20080191748A1

公开(公告)日：2008-08-14

申请号：US11958277

申请日：2007-12-17

Applicant: Sang Jin Byeon

Inventor： Sang Jin Byeon

IPC: H03K5/125

CPC classification number: G11C7/08 ,  G11C5/143 ,  G11C5/145 ,  G11C11/4091

Abstract: An apparatus for supplying an overdriving signal in a memory apparatus. The apparatus includes: a voltage detecting block that outputs a plurality of detection signals according to the level of an external voltage, and a pulse generator that outputs the overdriving signals having different pulse widths according to the plurality of detection signals.

Abstract translation: 一种用于在存储装置中提供过驱动信号的装置。 该装置包括：电压检测块，其根据外部电压的电平输出多个检测信号;以及脉冲发生器，其根据多个检测信号输出具有不同脉冲宽度的过驱动信号。

公开(公告)号：US07193920B2

公开(公告)日：2007-03-20

申请号：US11169949

申请日：2005-06-30

Applicant: Sang Jin Byeon ,  Kee Teok Park

Inventor： Sang Jin Byeon ,  Kee Teok Park

IPC: G11C5/14

CPC classification number: G11C5/14

Abstract: A semiconductor memory device generates a control signal for regulating a potential of an internal power voltage when an extended mode register is set to adjust an operating speed and a tWR (time to write recovery) of a chip. The semiconductor memory device comprises an extended mode register setting unit and an internal power voltage generating unit. When an internal circuit enters into a specific mode for high-speed operation, the extended mode register setting unit outputs a plurality of internal power control signals to regulate a potential of an internal power voltage of the internal circuit. The internal power voltage generating unit generates an internal power voltage by regulating the potential of the internal power voltage in response to the plurality of internal power control signals.

Abstract translation: 当扩展模式寄存器被设置以调整芯片的操作速度和tWR（写入恢复时间）时，半导体存储器件产生用于调节内部电源电压的电位的控制信号。 半导体存储器件包括扩展模式寄存器设置单元和内部电源电压产生单元。 当内部电路进入用于高速运行的特定模式时，扩展模式寄存器设置单元输出多个内部功率控制信号以调节内部电路的内部电源电压的电位。 内部电力电压产生单元通过响应于多个内部功率控制信号调节内部电力电压的电位而产生内部电力电压。