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    System and method for predicting cache performance
    31.
    发明授权
    System and method for predicting cache performance 有权
    用于预测缓存性能的系统和方法

    公开(公告)号：US06952664B1

    公开(公告)日：2005-10-04

    申请号：US09834342

    申请日：2001-04-13

    申请人： Tirthankar Lahiri ,  Juan R. Loaiza ,  Arvind Nithrakashyap ,  William H. Bridge

    发明人： Tirthankar Lahiri ,  Juan R. Loaiza ,  Arvind Nithrakashyap ,  William H. Bridge

    IPC分类号： G06F17/50 ,  G06G17/50

    CPC分类号： G06F17/5022

    摘要： A system and methods for simulating the performance (e.g., miss rate) of one or more caches. A cache simulator comprises a segmented list of buffers, with each buffer configured to store a data identifier and an identifier of the buffer's segment. Data references, which may be copied from an operational cache, are applied to the list to conduct the simulation. Initial estimates of each cache's miss rate include the number of references that missed all segments of the list plus the hits in all segments not part of the cache. A correction factor is generated from the ratio of actual misses incurred by the operational cache to the estimated misses for a simulated cache of the same size as the operational cache. Final predictions are generated by multiplying the initial estimates by the correction factor. The size of the operational cache may be dynamically adjusted based on the final predictions.

    摘要翻译： 用于模拟一个或多个高速缓存的性能（例如，错过率）的系统和方法。 缓存模拟器包括分段缓冲器列表，其中每个缓冲器被配置为存储数据标识符和缓冲器段的标识符。 可以从操作缓存复制的数据引用被应用于列表以进行模拟。 每个缓存的未命中率的初始估计包括丢失列表的所有段的引用数量加上不是高速缓存的一部分的所有段中的命中。 由操作缓存引起的实际未命中率与与操作缓存大小相同的模拟高速缓存的估计未命中的比率产生校正因子。 最终预测是通过将初始估计乘以校正因子而产生的。 可以基于最终预测来动态地调整操作高速缓存的大小。

    Automatically determining an optimal database subsection
    32.
    发明授权
    Automatically determining an optimal database subsection 有权

    公开(公告)号：US09063962B2

    公开(公告)日：2015-06-23

    申请号：US13842843

    申请日：2013-03-15

    申请人： John Raitto ,  Tirthankar Lahiri ,  Marie-Anne Neimat ,  Chih-Ping Wang

    发明人： John Raitto ,  Tirthankar Lahiri ,  Marie-Anne Neimat ,  Chih-Ping Wang

    IPC分类号： G06F17/30

    摘要： A method, apparatus, and system for automatically determining an optimal database subsection is provided. A database subsection is selected to optimize certain benefits when the database subsection is translated, transferred, and cached on an alternative database system, which may utilize a different technology or database engine that provides certain performance benefits compared to the original database system. Algorithms such as multi-path greedy selection and/or dynamic programming may provide optimal or near-optimal results. A host for the alternative database server may be shared with or otherwise located in close physical proximity to improve latency for a database application or client layer. Once the database subsection analysis is completed, a report may be generated and presented to the user, and an implementation script may also be created to automatically configure a client host to function as a cache or replacement system according various cache size configurations described in the report.

    Techniques for automated allocation of memory among a plurality of pools
    35.
    发明授权
    Techniques for automated allocation of memory among a plurality of pools 有权
    在多个池中自动分配存储器的技术

    公开(公告)号：US07783852B2

    公开(公告)日：2010-08-24

    申请号：US10746471

    申请日：2003-12-23

    申请人： Tirthankar Lahiri ,  Poojan Kumar ,  Brian Hirano ,  Arvind Nithrakashyap ,  Kant Patel ,  Kiran Goyal ,  Juan R. Loaiza

    发明人： Tirthankar Lahiri ,  Poojan Kumar ,  Brian Hirano ,  Arvind Nithrakashyap ,  Kant Patel ,  Kiran Goyal ,  Juan R. Loaiza

    IPC分类号： G06F12/00

    CPC分类号： G06F9/5016 ,  G06F12/023

    摘要： Allocation of memory is optimized across multiple pools of memory, based on minimizing the time it takes to successfully retrieve a given data item from each of the multiple pools. First data is generated that indicates a hit rate per pool size for each of multiple memory pools. In an embodiment, the generating step includes continuously monitoring attempts to access, or retrieve a data item from, each of the memory pools. The first data is converted to second data that accounts for a cost of a miss with respect to each of the memory pools. In an embodiment, the second data accounts for the cost of a miss in terms of time. How much of the memory to allocate to each of the memory pools is determined, based on the second data. In an embodiment, the steps of converting and determining are automatically performed, on a periodic basis.

    摘要翻译： 基于最小化从多个池中的每一个成功检索给定数据项所需的时间，内存分配在多个内存池之间进行了优化。 生成第一个数据，指示每个多个内存池的每个池大小的命中率。 在一个实施例中，生成步骤包括连续地监视从每个存储器池访问或检索数据项的尝试。 第一个数据被转换成相对于每个存储器池来计算缺失成本的第二数据。 在一个实施例中，第二数据考虑到时间方面的错过的成本。 基于第二数据确定分配给每个存储器池的存储器的多少。 在一个实施例中，周期性地自动执行转换和确定的步骤。

    PARTIAL KEY INDEXES
    36.
    发明申请
    PARTIAL KEY INDEXES 有权
    部分主要指标

    公开(公告)号：US20090157701A1

    公开(公告)日：2009-06-18

    申请号：US11956287

    申请日：2007-12-13

    申请人： Tirthankar Lahiri ,  Dheeraj Pandey ,  Juan R. Loaiza ,  Michael Zoll ,  Kiran B. Goyal ,  Neil J.S. Macnaughton

    发明人： Tirthankar Lahiri ,  Dheeraj Pandey ,  Juan R. Loaiza ,  Michael Zoll ,  Kiran B. Goyal ,  Neil J.S. Macnaughton

    IPC分类号： G06F17/30

    CPC分类号： G06F17/30327

    摘要： A partial reverse key index is described, which allows distributed contention as resources vie to insert data into an index as well as allows range scans to be performed on the index. To do so, before an index entry for a key value is inserted into an index, the key value is transformed using a transformation operation that affects a subset of the order of the key value. The index entry is then inserted based on the transformed key value. Because the transformation operation affects the order of the key value, the transformed values associated with two consecutive key values will not necessarily be consecutive. Therefore, the index entries associated with the consecutive key values may be inserted into unrelated portions of the index.

    摘要翻译： 描述了部分反向密钥索引，其允许分布式争用作为将数据插入到索引中的资源，并且允许在索引上执行范围扫描。 为此，在将键值的索引条目插入索引之前，将使用影响键值顺序子集的转换操作来转换键值。 然后基于转换的键值插入索引条目。 由于转换操作影响键值的顺序，与两个连续的键值相关联的变换值不一定是连续的。 因此，可以将与连续键值相关联的索引条目插入索引的无关部分。

    Managing memory in a system that includes a shared memory area and a private memory area
    38.
    发明申请
    Managing memory in a system that includes a shared memory area and a private memory area 有权
    在包含共享内存区域和专用内存区域的系统中管理内存

    公开(公告)号：US20080235481A1

    公开(公告)日：2008-09-25

    申请号：US11726060

    申请日：2007-03-20

    申请人： Bharat C.V. Baddepudi ,  Tirthankar Lahiri ,  Kiran B. Goyal ,  Benoit Dageville ,  Siddhartha Roychowdhury ,  Brian Hirano ,  Balasubramanian Narasimhan

    发明人： Bharat C.V. Baddepudi ,  Tirthankar Lahiri ,  Kiran B. Goyal ,  Benoit Dageville ,  Siddhartha Roychowdhury ,  Brian Hirano ,  Balasubramanian Narasimhan

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0284 ,  G06F9/52

    摘要： A method and apparatus for auto-tuning memory is provided. Memory on a computer system comprises at least one shared memory area and at least one private memory area. Addresses in the shared memory area are accessible to multiple processes. Addresses in the private memory area are dedicated to individual processes. Initially, a division in the amount of memory is established between the shared and private memory areas. Subsequently, a new division is determined. Consequently, memory from one memory area is “given” to the other memory area. In one approach, such sharing is achieved by causing the shared and private memory areas to be physically separate from each other both before and after a change in the division. The division of the amount of memory may be changed to a new division by deallocating memory from one of the memory areas and allocating that memory to the other of the memory areas.

    摘要翻译： 提供了一种用于自动调谐存储器的方法和装置。 计算机系统上的存储器包括至少一个共享存储器区域和至少一个专用存储器区域。 共享内存区域中的地址可以访问多个进程。 专用内存区域中的地址专用于各个进程。 最初，在共享和专用存储区之间建立了存储量的划分。 随后，确定了一个新的部门。 因此，来自一个存储器区域的存储器被“给予”另一个存储器区域。 在一种方法中，这种共享是通过使分区和专用存储器区域在分区改变之前和之后彼此物理上分开来实现的。 通过从存储区域之一释放存储器并将该存储器分配给存储区域中的另一个，可以将存储量的划分改变为新的划分。

    Mean time to recover (MTTR) advisory
    40.
    发明授权
    Mean time to recover (MTTR) advisory 有权
    平均恢复时间（MTTR）咨询

    公开(公告)号：US07020599B1

    公开(公告)日：2006-03-28

    申请号：US10017337

    申请日：2001-12-13

    申请人： Qiang Cao ,  Sushil Kumar ,  Tirthankar Lahiri ,  Yunrui Li ,  Gianfranco Putzolu

    发明人： Qiang Cao ,  Sushil Kumar ,  Tirthankar Lahiri ,  Yunrui Li ,  Gianfranco Putzolu

    IPC分类号： G06F9/45

    CPC分类号： G06F11/3457 ,  G06F17/30306 ,  G06F2201/86 ,  Y10S707/99943 ,  Y10S707/99953

    摘要： A method for simulating different MTTR settings includes determining a simulated MTTR setting and providing a simulated checkpoint queue. The simulated checkpoint queue is associated with the simulated MTTR setting and is an ordered list of one or more elements. Each element represents a buffer, and the ordered list has a head and a tail. The method also includes providing a simulated write counter associated with the simulated MTTR setting. The method further includes, in response to detecting a change to a first buffer, checking if the first buffer is represented in the simulated checkpoint queue. If the first buffer is not represented in the simulated checkpoint queue, an element that represents the first buffer is linked to the tail of the simulated checkpoint queue. An MTTR advisory system includes a memory, one or more processors coupled to the memory, a simulated MTTR setting, a simulated checkpoint queue, and a simulated write counter. The simulated MTTR setting is maintained in the memory. The simulated checkpoint queue is maintained in the memory and associated with the simulated MTTR setting. The simulated write counter is also maintained in the memory, and is associated with the simulated MTTR setting. The simulated write counter provides a count of the number of times an element is removed from the simulated checkpoint queue, wherein the element is removed from the simulated checkpoint queue in response to a write out of a buffer from volatile memory and storing in nonvolatile memory.

    摘要翻译： 用于模拟不同MTTR设置的方法包括确定模拟MTTR设置并提供模拟检查点队列。 模拟的检查点队列与模拟的MTTR设置相关联，并且是一个或多个元素的有序列表。 每个元素表示一个缓冲区，有序列表有一个头和尾。 该方法还包括提供与模拟的MTTR设置相关联的模拟写入计数器。 该方法还包括响应于检测到对第一缓冲器的改变，检查在模拟检查点队列中是否表示第一缓冲器。 如果模拟检查点队列中没有表示第一个缓冲区，则表示第一个缓冲区的元素链接到模拟检查点队列的尾部。 MTTR咨询系统包括存储器，耦合到存储器的一个或多个处理器，模拟MTTR设置，模拟检查点队列和模拟写入计数器。 模拟的MTTR设置保留在内存中。 模拟检查点队列保存在存储器中并与模拟的MTTR设置相关联。 模拟写计数器也保存在存储器中，并与模拟的MTTR设置相关联。 仿真写入计数器提供从模拟检查点队列中删除元素的次数的计数，其中响应于从易失性存储器写入缓冲器并存储在非易失性存储器中，将元件从模拟检查点队列中移除。