公开(公告)号：US07188323B2

公开(公告)日：2007-03-06

申请号：US10892022

申请日：2004-07-15

Applicant: Seongmoon Wang ,  Wei Li ,  Srimat T. Chakradhar

Inventor： Seongmoon Wang ,  Wei Li ,  Srimat T. Chakradhar

IPC: G06F17/50

CPC classification number: G01R31/318544

Abstract: Disclosed is a method and apparatus for improved delay fault testing by optimizing the order of scan cells in a scan chain. The order of the scan cells is determined by using a cost value for an order of scan cells, the cost value being computed from costs assigned to orderings of individual pairs of scan cells. These costs can be based on the number of faults that are untestable when the pair of scan cells are placed consecutively in the scan chain. The disclosed techniques allow for enhanced delay fault coverage by rearranging scan flip-flops without increasing routing overhead.

Abstract translation: 公开了一种通过优化扫描链中扫描单元的顺序来改进延迟故障测试的方法和装置。 通过使用扫描单元的顺序的成本值来确定扫描单元的顺序，成本值是根据分配给单个扫描单元对的顺序的成本计算的。 这些成本可以基于在扫描链中连续放置一对扫描单元时不可测量的故障的数量。 所公开的技术允许通过重新排列扫描触发器而不增加路由开销来增强延迟故障覆盖。

公开(公告)号：US20060112320A1

公开(公告)日：2006-05-25

申请号：US11095222

申请日：2005-03-31

Applicant: Kedarnath Balakrishnan ,  Seongmoon Wang ,  Srimat Chakradhar

Inventor： Kedarnath Balakrishnan ,  Seongmoon Wang ,  Srimat Chakradhar

IPC: G01R31/28 ,  G06F11/00

CPC classification number: G01R31/318335 ,  G01R31/318371

Abstract: The present invention is directed to a logic testing architecture with an improved decompression engine that compresses the seeds of a linear test pattern generator in a manner that is independent of the test pattern set.

Abstract translation: 本发明涉及具有改进的解压缩引擎的逻辑测试架构，其以独立于测试模式集的方式压缩线性测试模式发生器的种子。

公开(公告)号：US20060015787A1

公开(公告)日：2006-01-19

申请号：US10891618

申请日：2004-07-15

Applicant: Seongmoon Wang ,  Srimat Chakradhar

Inventor： Seongmoon Wang ,  Srimat Chakradhar

IPC: G01R31/28

CPC classification number: G01R31/318335 ,  G01R31/318385 ,  G01R31/31921

Abstract: The present invention is directed to a logic testing architecture with an improved decompression engine and a method of decompressing scan chains for testing logic circuits.

Abstract translation: 本发明涉及具有改进的解压缩引擎的逻辑测试架构和用于测试逻辑电路的解压缩扫描链的方法。

公开(公告)号：US20050235183A1

公开(公告)日：2005-10-20

申请号：US10892022

申请日：2004-07-15

Applicant: Seongmoon Wang ,  Wei Li ,  Srimat Chakradhar

Inventor： Seongmoon Wang ,  Wei Li ,  Srimat Chakradhar

IPC: G01R31/28 ,  G01R31/3185 ,  G06F17/50

CPC classification number: G01R31/318544

Abstract: The present invention is directed to improved delay fault testing by optimizing the order of scan cells in a scan chain.

Abstract translation: 本发明旨在通过优化扫描链中的扫描单元的顺序来改进延迟故障测试。

公开(公告)号：US06886124B2

公开(公告)日：2005-04-26

申请号：US09805899

申请日：2001-03-15

Applicant: Seongmoon Wang

Inventor： Seongmoon Wang

IPC: G01R31/28 ,  G01R31/3181 ,  G01R31/3183 ,  G01R31/3185 ,  G06F11/22 ,  G06F11/263 ,  G06F11/27 ,  G06F11/00

CPC classification number: G06F11/27 ,  G01R31/31813 ,  G01R31/318547 ,  G06F11/263

Abstract: Techniques for generating a test set for hard to detect faults is disclosed. A set of hard to detect faults is identified. A test set for the hard to detect faults is generated by using an improved automatic test pattern generator. The improved automatic test pattern generator is adapted to consider hardware overhead and test sequence lengths, the hardware overheads being incurred when each new testcube is added to the test set. Parallel and serial type test per scan built-in self test circuits designed and adapted to use the disclosed improved automatic test pattern generator are also disclosed.

Abstract translation: 公开了用于生成难以检测故障的测试装置的技术。 确定了一组难以检测的故障。 通过使用改进的自动测试模式发生器产生难以检测故障的测试集。 改进的自动测试模式生成器适用于考虑硬件开销和测试序列长度，当将每个新的测试器添加到测试集中时，会​​产生硬件开销。 还公开了并行和串联型测试，每个扫描内置的自检电路设计并适用于使用所公开的改进的自动测试图案发生器。