公开(公告)号：US06306749B1

公开(公告)日：2001-10-23

申请号：US09327874

申请日：1999-06-08

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L214763

CPC classification number: H01L24/05 ,  H01L24/45 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05599 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2224/48 ,  H01L2924/00

Abstract: A bond pad structure for use in wire bonding application during the packaging operation of semiconductor devices which contains a bond frame structure for holding the bond pad in place to prevent bond pad peel-off problem. The bond pad structure is a laminated structure containing a top dielectric layer, a metal bond pad layer, a middle dielectric layer, and an underlying layer formed above a wafer surface. The bond frame structure, which is formed in a spaced apart relationship from the metal bond pad layer contains a plurality of island elements formed on top of the middle dielectric layer and an interconnected frame element formed on top of the top dielectric layer. The frame element contains a portion which overlaps with a portion of the metal bond pad layer, so as to exert a downward force to prevent the metal bond pad layer from peeling off. Each of the island elements is respectively connected to the underlying layer and the frame element by one or a plurality of hole-fills, which can contain an appropriate hole-material such as tungsten plus or can be filled with the same material constituting the layer overlaying them. The underlying layer can be a metal layer, a semiconductor layer such as a polysilicon layer, or any material layer which has good adhesion with the hole fill material.

Abstract translation: 一种用于在半导体器件的封装操作期间的引线接合应用中的接合焊盘结构，其包含用于将接合焊盘保持在适当位置以防止接合焊盘剥离问题的接合框架结构。 接合焊盘结构是包含顶部电介质层，金属焊盘层，中间电介质层和形成在晶片表面上的下层的层压结构。 与金属接合焊盘层间隔开的结合框架结构包含形成在中间电介质层的顶部上的多个岛状元件和形成在顶部电介质层顶部的互连框架元件。 框架元件包含与金属接合焊盘层的一部分重叠的部分，以便施加向下的力以防止金属焊盘层剥离。 每个岛元件分别通过一个或多个孔填充物连接到下层和框架元件，孔填充物可以包含诸如钨的合适的空穴材料，或者可以填充构成覆盖层的相同材料 他们。 下层可以是金属层，诸如多晶硅层的半导体层，或与填充孔材料具有良好粘附性的任何材料层。

公开(公告)号：US06246223B1

公开(公告)日：2001-06-12

申请号：US08984886

申请日：1997-12-04

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: G01R2302

CPC classification number: G01R23/10 ,  G01R31/2824

Abstract: A method is provided for use on a parametric tester that allows the parametric tester to more effectively and precisely measure the output frequency of a periodic pulse signal generating means. The first step is to down convert the output frequency of the periodic pulse signal generating means to about 1 Hz. Then, the frequency-downconverted pulse train is sampled to thereby obtain a series of sampled signals In accordance with the magnitudes of the sampled signals, the sampled signals are registered to be at either a high-level state, an low-level state, or a intermediate-level state. Then, the integration time and the delay time involved in the sampling process are registered. The sampling process is continued until at least two sampled signals at the low-level state are registered. Based on these parameters, a delta transition time for the first intermediate-level state and a second delta transition time for the second intermediate-level state can be obtained. Further, the length of the period from the occurrence of the first intermediate-level state to the occurrence of the second intermediate-level state is computed based on the number of the occurrences of pulse transitions during this period. Based on the foregoing parameters, the frequency of the frequency-downconverted pulse train can be obtained, which then allows the output frequency of the periodic pulse signal generating means to be obtained.

Abstract translation: 提供了一种在参数测试仪上使用的方法，其允许参数测试器更有效和精确地测量周期性脉冲信号产生装置的输出频率。 第一步是将周期性脉冲信号发生装置的输出频率降低到约1Hz。 然后，对降频转换脉冲串进行采样，从而获得一系列采样信号。根据采样信号的幅度，采样信号被登记为处于高电平状态，低电平状态或 中级国家。 然后，记录采样过程所涉及的积分时间和延迟时间。 采样过程持续到低电平状态的至少两个采样信号被注册。 基于这些参数，可以获得第一中间级状态的增量转换时间和第二中间级状态的第二增量转换时间。 另外，从该第一中间状态的发生到第二中间电平状态的发生的期间的长度是根据该期间的脉冲转移的次数计算的。 基于上述参数，可以获得频率下变频脉冲序列的频率，从而可以获得周期性脉冲信号发生装置的输出频率。

公开(公告)号：US06178549B1

公开(公告)日：2001-01-23

申请号：US09041483

申请日：1998-03-12

Applicant: Shi-Tron Lin ,  Meng-Tsang Wu

Inventor： Shi-Tron Lin ,  Meng-Tsang Wu

IPC: G06F9445

CPC classification number: G11C29/88

Abstract: A memory writer has the capability to modify the machine code according to the defective memory-cell locations, such that the modified code functionally bypasses all defective memory-cell addresses upon program execution. The machine code is modified without re-compilation of the microprogram, instead, it is modified by inserting jump machine-code instructions directly between instruction steps, and to insert dummy bytes between adjacent memory space allocations for symbols definition. The machine code is further modified to take into account of the effect of the insertion of additional codes on the instruction within the machine code that involve the address referencing. The modified machine code, when written to the partially defective memory, performs identical routines while bypassing all defective memory-cell addresses. The present invention is useful for writing a microprogram in non-volatile memories, such as EPROM, EEPROM or Flash/EEPROM. It is also useful in loading a microprogram in volatile memories like SRAM, DRAM, etc.

Abstract translation: 存储器写入器具有根据有缺陷的存储单元位置修改机器代码的能力，使得修改的代码在程序执行时功能地绕过所有有缺陷的存储器单元地址。 机器代码被修改而不重新编译微程序，而是通过直接在指令步骤之间插入跳转机器代码指令来修改，并在相邻的存储器空间分配之间插入伪字节用于符号定义。 进一步修改机器代码以考虑到附加代码插入涉及地址引用的机器代码内的指令的影响。 修改的机器代码在写入部分缺陷的存储器时，执行相同的程序，同时绕过所有有缺陷的存储单元地址。 本发明对于将微程序写入诸如EPROM，EEPROM或闪存/ EEPROM的非易失性存储器中是有用的。 在像SRAM，DRAM等易失性存储器中加载微程序也很有用。

公开(公告)号：US6141768A

公开(公告)日：2000-10-31

申请号：US41226

申请日：1998-03-12

Applicant: Shi-Tron Lin ,  Ding-Yuan Yang

Inventor： Shi-Tron Lin ,  Ding-Yuan Yang

IPC: G06F11/22 ,  G11C29/00 ,  G11C29/44 ,  G06F11/00

CPC classification number: G11C29/76 ,  G06F11/2284 ,  G11C29/44

Abstract: A computer system is provided which performs a self-test of the memory cells of a memory device prior to loading of a computer program into the memory device, so as to determine the locations of defective memory cells. During loading of the computer program, each instruction step, data block and stack declaration is decoded, and the present invention creates and inserts a jump instruction into the original program code to bypass any defective memory cells without interrupting the intended operation of the instruction steps that are loaded into the memory. The loaded program code is then modified to correct any address-referencing that may be changed due to the insertion of the jump instructions. The present invention can even periodically perform a self-test procedure during the normal operation of the computer system so as to locate new defective memory cells and to modify the program code to bypass these newly-located defective memory cells.

Abstract translation: 提供一种计算机系统，其在将计算机程序加载到存储器件之前对存储器件的存储器单元执行自检，以便确定有缺陷的存储器单元的位置。 在加载计算机程序期间，解码每个指令步骤，数据块和堆栈声明，并且本发明创建并将跳转指令插入到原始程序代码中以绕过任何有缺陷的存储器单元而不中断指令步骤的预期操作， 被加载到内存中。 然后修改加载的程序代码以校正任何可能由于插入跳转指令而改变的地址引用。 本发明甚至可以在计算机系统的正常操作期间周期性地执行自检程序，以便定位新的有缺陷的存储器单元并且修改程序代码以绕过这些新定位的有缺陷的存储器单元。

公开(公告)号：US6108797A

公开(公告)日：2000-08-22

申请号：US988574

申请日：1997-12-11

Applicant: Shi-Tron Lin ,  Ding-Yuan Yang ,  Meng-Tsang Wu

Inventor： Shi-Tron Lin ,  Ding-Yuan Yang ,  Meng-Tsang Wu

IPC: G06F9/445 ,  G11C29/00 ,  G06F12/02

CPC classification number: G06F9/445 ,  G11C29/76 ,  G11C29/88

Abstract: When loading executable machine code into memories, the defective memory locations can be bypassed by properly inserting jump instructions or dummy memory allocation instructions in the program code. Prior to loading the executable code into the memories, defective memory locations are checked and recorded first. The source program code are analyzed to see which instruction step will fall into defective memory locations. Dummy memory space allocation instructions or additional jump instructions, are inserted in the original micro code, such that defective memory locations can be bypassed when the modified program code is loaded into the working memory space. The present invention is useful for loading executable programs in programmable and verifiable memories, such as Flash/EEPROM, EPROM, SRAM and DRAM, etc.

Abstract translation: 当将可执行机器码加载到存储器中时，可以通过在程序代码中适当地插入跳转指令或虚拟存储器分配指令来绕过有缺陷的存储单元。 在将可执行代码加载到存储器之前，首先检查和记录缺陷存储单元。 分析源程序代码，以查看哪个指令步骤将落入有缺陷的存储器位置。 虚拟存储器空间分配指令或附加跳转指令被插入到原始微代码中，使得当修改的程序代码被加载到工作存储器空间中时可以绕过有缺陷的存储器位置。 本发明可用于在诸如闪存/ EEPROM，EPROM，SRAM和DRAM等的可编程和可验证存储器中加载可执行程序。

公开(公告)号：US6083797A

公开(公告)日：2000-07-04

申请号：US324858

申请日：1999-06-03

Applicant: Shyh-Chyi Wong ,  Shi-Tron Lin

Inventor： Shyh-Chyi Wong ,  Shi-Tron Lin

IPC: H01L21/336 ,  H01L21/762 ,  H01L21/8238

CPC classification number: H01L29/66651 ,  H01L21/76224 ,  H01L21/823878

Abstract: An integrated semiconductor device includes a substrate having a buried shallow trench isolation structure and an epitaxial layer disposed over the substrate and the buried shallow trench isolation structure. The epitaxial layer includes a shallow trench isolation structure that extends over the buried shallow trench isolation structure in the substrate to substantially reduce leakage current in the substrate to prevent device latch-up.

公开(公告)号：US5982601A

公开(公告)日：1999-11-09

申请号：US126196

申请日：1998-07-30

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L27/02 ,  H02H9/04 ,  H02H3/22

CPC classification number: H01L27/0262 ,  H01L29/87 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection structure for an integrated circuit constructed on a semiconductor substrate of a first type (P) comprises a semiconductor controlled rectifier (SCR) formed on the substrate and coupled to the integrated circuit and a transient voltage oscillation circuit, the SCR including a first region of a second type (nwell) formed within the semiconductor substrate and a second region of the first type (P) positioned within the first region, the transient voltage oscillation circuit being coupled to the first region and is adapted to forward-bias a junction between the second region and the first region (P+/nwell junction) at least once during an ESD transient period for earlier triggering the SCR during the ESD event, thereby improving the ESD performance of the SCR ESD protection circuit used for protecting a power bus of the integrated circuit or an IC pin connected to the integrated circuit during an ESD event.

Abstract translation: 构成在第一类型（P）的半导体衬底上的集成电路的静电放电（ESD）保护结构包括形成在衬底上并与集成电路耦合的半导体可控整流器（SCR）和瞬态电压振荡电路， SCR包括形成在半导体衬底内的第二类型（nwell）的第一区域和位于第一区域内的第一类型（P）的第二区域，瞬态电压振荡电路耦合到第一区域并适于向前 在ESD过渡期间至少一次在第二区域和第一区域（P + / nwell结）之间的连接点，以便在ESD事件期间较早触发SCR，从而提高用于保护的SCR ESD保护电路的ESD性能 在ESD事件期间集成电路的电源总线或连接到集成电路的IC引脚。

公开(公告)号：US5852541A

公开(公告)日：1998-12-22

申请号：US955505

申请日：1997-10-22

Applicant: Shi-Tron Lin ,  Hao-Luen Tien ,  Shyh-Chyi Wong

Inventor： Shi-Tron Lin ,  Hao-Luen Tien ,  Shyh-Chyi Wong

IPC: H01L27/02 ,  H02H9/04 ,  H02H3/22

CPC classification number: H01L27/0248 ,  H02H9/046

Abstract: A transient oscillating circuit is provided to generate a series of current pulses for triggering turn-on of an ESD protection device. As VDD-to-VSS voltage increases rapidly in the initial ESD event, the series of current pulses injects minority carriers into the pwell of an NMOS transistor via an adjacent n+/pwell diode. These minority carriers flow toward the drain-substrate junction of the NMOS transistor such that the NMOS transistor is triggered at a trigger voltage lower than that provided by the prior arts. The present invention improves the ESD performance of an ESD protection device, such as a MOSFET or bipolar transistor, which is provided for protecting the power bus or IC pins during an ESD event.

Abstract translation: 提供瞬态振荡电路以产生用于触发ESD保护装置的导通的一系列电流脉冲。 由于VDD-VSS电压在初始ESD事件中迅速增加，所以一系列电流脉冲通过相邻的n + / pwell二极管将少数载流子注入到NMOS晶体管的阱中。 这些少数载流子流向NMOS晶体管的漏极 - 衬底结，使得在比现有技术提供的触发电压低的触发电压下触发NMOS晶体管。 本发明改进了ESD保护装置（例如MOSFET或双极晶体管）的ESD性能，其被提供用于在ESD事件期间保护电源总线或IC引脚。

公开(公告)号：US20110232214A1

公开(公告)日：2011-09-29

申请号：US13070435

申请日：2011-03-23

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: E04F11/022

CPC classification number: E04F11/0201

Abstract: A method of converting a traditional staircase into a dual-use staircase, for reducing the stepping height and knee stress in stairs climbing and descending, comprises: providing a plurality of lifting modules and a plurality of extending modules; connecting the plurality of lifting and extending modules in pairs to the original steps respectively; and optionally connecting a plurality of dividers in between said lifting and extending modules respectively.The dual-use staircase structure reduces the step rise by half, while keeping the total run about the same. It allows healthy people to walk in a full-step domain, while allowing people with knee concerns to walk on a half-step domain. The dual-use staircase may include dividers with lateral openings to facilitate reverse turning halfway during ascending or descending of the staircase.

Abstract translation: 一种将传统楼梯转换为双用途楼梯的方法，用于降低台阶爬坡和降落中的踏板高度和膝盖应力，包括：提供多个提升模块和多个延伸模块; 将多个提升和延伸模块成对分别连接到原始步骤; 并且可选地分别在所述提升和延伸模块之间连接多个分隔件。 双用途楼梯结构减少了一半，同时保持总的运行大致相同。 它可以让健康的人走在一个全面的领域，同时让膝盖关心的人走在一个半步的领域。 双用途楼梯可包括具有横向开口的分隔件，以便在楼梯上升或下降期间中途进行倒车。

公开(公告)号：US07102195B2

公开(公告)日：2006-09-05

申请号：US09740017

申请日：2000-12-20

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L23/62

CPC classification number: H01L27/0259 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor layer, a source region formed in the layer, a drain region formed in the layer, a channel region in the layer between the source and drain regions, and a gate over the channel region. One or more islands are distributed either symmetrically or non-symmetrically in and along the drain region. The islands can be formed of polysilicon or a field oxide.