公开(公告)号：US20120241747A1

公开(公告)日：2012-09-27

申请号：US13511661

申请日：2010-07-09

申请人： Chikao Yamasaki ,  Tetsuo Kikuchi ,  Shinya Tanaka ,  Junya Shimada

发明人： Chikao Yamasaki ,  Tetsuo Kikuchi ,  Shinya Tanaka ,  Junya Shimada

IPC分类号： H01L29/786

CPC分类号： H01L27/124 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G11C19/184 ,  G11C19/28 ,  H01L29/41733 ,  H01L29/42384

摘要： The present invention provides a shift register and a display device, each of which operates stably. The present invention relate to a shift register, comprising a thin-film transistor which includes a source electrode, a drain electrode, and a gate electrode, the thin-film transistor being a bottom gate thin-film transistor which includes a comb-shaped source/drain structure, the gate electrode being provided with at least one of a cut and an opening in at least one of a region overlapping with the source electrode and a region overlapping with the drain electrode.

摘要翻译： 本发明提供了一种移位寄存器和显示装置，每个都能稳定地工作。 本发明涉及一种移位寄存器，包括一个薄膜晶体管，它包括一个源电极，一个漏电极和一个栅电极，该薄膜晶体管是一个底栅薄膜晶体管，它包括一个梳形源 漏极结构，栅电极在与源电极重叠的区域和与漏电极重叠的区域中的至少一个区域中设置有切割开口和开口中的至少一个。

公开(公告)号：US20120168762A1

公开(公告)日：2012-07-05

申请号：US13394621

申请日：2010-05-21

申请人： Tetsuo Kikuchi ,  Shinya Tanaka ,  Junya Shimada ,  Chikao Yamasaki

发明人： Tetsuo Kikuchi ,  Shinya Tanaka ,  Junya Shimada ,  Chikao Yamasaki

IPC分类号： H01L29/786

CPC分类号： H01L27/3276 ,  G02F1/133553 ,  G02F1/13452 ,  G02F1/13454 ,  G02F1/13458 ,  G02F2001/13629 ,  H01L27/124

摘要： A second stem wires (17c), formed by a reflective pixel electrode layer formed as a different layer from first stem wires (17a), is provided in such a way as to extend along a long side of its adjacent one of the first stem wires (17a).This makes it possible to achieve a TFT array substrate (1) on which a gate drive circuit (15) and its wires (17a, 17b, 17c, 18) have been monolithically formed, wherein the width of a frame part in which the a gate drive circuit (15) and its wires (17a, 17b, 17c, 18) are formed can be reduced.

摘要翻译： 由与第一杆线（17a）形成为不同层的反射像素电极层形成的第二杆线（17c）设置成沿其相邻的第一杆线的长边延伸 （17a）。 这使得可以实现其栅极驱动电路（15）及其导线（17a，17b，17c，18）已经被整体地形成在其上的框架部分的宽度，其中a 栅极驱动电路（15）及其导线（17a，17b，17c，18）可以被形成。

公开(公告)号：US20120162179A1

公开(公告)日：2012-06-28

申请号：US13393812

申请日：2010-04-13

申请人： Shinya Tanaka ,  Tetsuo Kikuchi ,  Junya Shimada ,  Takuya Watanabe

发明人： Shinya Tanaka ,  Tetsuo Kikuchi ,  Junya Shimada ,  Takuya Watanabe

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/0286

摘要： In a liquid crystal display device provided with a monolithic gate driver, a panel frame area is to be reduced as compared with a conventional configuration so that the device size can be reduced. In a region on an array substrate located outside of a display region, a third metal (503) is formed as a metal film in addition to a source metal (501) and a gate metal (502). The source metal (501) forms a wiring pattern that includes source electrodes of thin film transistors disposed in a pixel circuit and a gate driver, and the gate metal (502) forms a wiring pattern that includes gate electrodes of the thin film transistors. The third metal (503) is electrically connected to at least one of the source metal (501) and the gate metal (502) through a contact.

摘要翻译： 在具有单片栅极驱动器的液晶显示装置中，与传统的结构相比，面板框架区域将被减小，从而可以减小装置的尺寸。 在位于显示区域外部的阵列基板上的区域中，除了源极金属（501）和栅极金属（502）之外，还形成第三金属（503）作为金属膜。 源极金属（501）形成包括设置在像素电路中的薄膜晶体管的源电极和栅极驱动器的布线图案，并且栅极金属（502）形成包括薄膜晶体管的栅电极的布线图案。 第三金属（503）通过触点与源极金属（501）和栅极金属（502）中的至少一个电连接。

公开(公告)号：US20120032615A1

公开(公告)日：2012-02-09

申请号：US13264828

申请日：2009-12-25

申请人： Tetsuo Kikuchi ,  Shinya Tanaka ,  Chikao Yamasaki ,  Junya Shimada

发明人： Tetsuo Kikuchi ,  Shinya Tanaka ,  Chikao Yamasaki ,  Junya Shimada

IPC分类号： H05B37/02 ,  G11C19/28

CPC分类号： G09G3/20 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2330/021 ,  G11C19/28

摘要： Provided is a shift register configured by cascade connecting unit circuits each including a bootstrap circuit. In at least one example embodiment, for the unit circuits, a time period during which a transistor is in an ON state and a clock signal is high level corresponds to a clock passing period. Among transistors whose one conduction terminal is connected to a gate of the transistor, channel lengths of transistors configured such that a low-level potential is fed to gates of the transistors to turn the transistors to an OFF state in the clock passing period and that a low-level potential is applied to the conduction terminal of the transistors in the clock passing period are made longer than the channel length of the transistor. With this, it is possible to reduce a leakage current in the clock passing period, and to prevent the fluctuation of a gate potential of the transistor and dullness in an output signal from occurring.

摘要翻译： 提供一种移位寄存器，其通过级联连接单元电路来构成，每个单元电路包括自举电路。 在至少一个示例性实施例中，对于单元电路，晶体管处于导通状态和时钟信号为高电平的时间段对应于时钟传递周期。 在其一个导通端子连接到晶体管的栅极的晶体管中，晶体管的沟道长度被配置为使得低电平电位被馈送到晶体管的栅极，以在晶体管的时钟通过期间将晶体管转换为截止状态，并且 在晶体管的导通端子中施加低电位电位使晶体管的通过时间长于晶体管的沟道长度。 由此，可以减小时钟通过期间的漏电流，并且防止晶体管的栅极电位的波动和输出信号中的钝度发生。

公开(公告)号：US08723845B2

公开(公告)日：2014-05-13

申请号：US13574049

申请日：2010-11-26

申请人： Shinya Tanaka ,  Tetsuo Kikuchi ,  Junya Shimada ,  Masahiro Yoshida ,  Isao Ogasawara ,  Satoshi Horiuchi

发明人： Shinya Tanaka ,  Tetsuo Kikuchi ,  Junya Shimada ,  Masahiro Yoshida ,  Isao Ogasawara ,  Satoshi Horiuchi

IPC分类号： G06F3/038

CPC分类号： G09G3/3688 ,  G09G2300/0413 ,  G09G2310/0297 ,  G09G2330/08 ,  H01L27/12 ,  H01L27/124 ,  H01L29/41733

摘要： A signal distribution circuit (3) includes (i) a redundancy TFT element (8) provided so as to have a channel width identical to those of driving TFT elements (7), (ii) first redundancy lines (9a, 9b), (iii) a second redundancy line (10), and (iv) a third redundancy line (11). It is therefore possible to provide a liquid crystal display device including the signal distribution circuit (3) in which, even in a case where a leaking part (a defect part) is generated in any of the driving TFT elements (7), it does not take long to restore the leaking part, and productivity can be improved, the driving TFT elements (7) keeping respective channel widths identical to one another even after the leaking part is restored.

摘要翻译： 信号分配电路（3）包括（i）设置为具有与驱动TFT元件（7）相同的沟道宽度的冗余TFT元件（8），（ii）第一冗余线（9a，9b），（ iii）第二冗余线（10），和（iv）第三冗余线（11）。 因此，可以提供一种包括信号分配电路（3）的液晶显示装置，其中即使在任何驱动TFT元件（7）中产生泄漏部分（缺陷部分）的情况下，也可以 即使在泄漏部分恢复之后，驱动TFT元件（7）保持各个通道宽度彼此相同，也不会耗费时间来恢复泄漏部分，并且可以提高生产率。

公开(公告)号：US08686980B2

公开(公告)日：2014-04-01

申请号：US13521308

申请日：2010-12-01

申请人： Masahiro Yoshida ,  Isao Ogasawara ,  Satoshi Horiuchi ,  Takaharu Yamada ,  Shinya Tanaka ,  Tetsuo Kikuchi

发明人： Masahiro Yoshida ,  Isao Ogasawara ,  Satoshi Horiuchi ,  Takaharu Yamada ,  Shinya Tanaka ,  Tetsuo Kikuchi

IPC分类号： G06F3/038 ,  G09G5/00

CPC分类号： G02F1/13454 ,  G02F1/13458 ,  G02F2001/136263 ,  H01L27/124

摘要： A gate driving circuit (60) separated into a plurality of stages (ST) is provided. In each of the stages (ST), TFT elements (T1) through (T4) are provided, branch lines (78) that connect clock lines (72, 74) to the TFT elements are provided. Junction lines (79A, 79B) are each extended from the branch line (78A) of interest to electrically connect the branch line (78A) of interest to the TFT elements (T2, T4) provided in the stage (ST(j)) different from the stage (ST (j−1)) where the TFT elements (T1, T3) connected to the branch line (78A) of interest are provided.

摘要翻译： 提供分离为多个级（ST）的栅极驱动电路（60）。 在各级（ST）中，设置TFT元件（T1）至（T4），将时钟线（72,74）连接到TFT元件的支线（78）设置。 各接线（79A，79B）各自从感兴趣的支线（78A）延伸，将感兴趣的分支线（78A）电连接到设置在台（ST（j））中的TFT元件（T2，T4）不同 提供与感兴趣的分支线路（78A）连接的TFT元件（T1，T3）的级（ST（j-1））。

公开(公告)号：US08531224B2

公开(公告)日：2013-09-10

申请号：US13501215

申请日：2010-07-15

申请人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Takaharu Yamada ,  Satoshi Horiuchi ,  Chikao Yamasaki ,  Kei Ikuta

发明人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Takaharu Yamada ,  Satoshi Horiuchi ,  Chikao Yamasaki ,  Kei Ikuta

IPC分类号： H03K3/00

CPC分类号： G09G3/3685 ,  G09G2310/0275 ,  G09G2310/0286 ,  G11C19/287

摘要： An object is shortening a clock fall-rise period while suppressing an increase in a circuit area, an increase in current consumption, and a cost increase, without generating an abnormal operation, in a shift register within a monolithic gate driver.In a shift register (410) that operates based on four-phase clock signals, including two-phase clock signals (GCK1, GCK3) that are provided to odd-order stages and two-phase clock signals (GCK2, GCK4) that are provided to even-order stages, of which phases are shifted by 90 degrees from each other, a potential of a first clock (CKA) appears as a potential of a scanning signal (GOUT), when a potential of a first node is at a high level, in each stage. In this configuration, the potential of the first node included in each stage is set to a high level based on a pulse of a scanning signal outputted from a pre-stage, and is set to a low level based on a pulse of a scanning signal outputted from a third stage after a stage concerned.

摘要翻译： 目的是在单片门驱动器内的移位寄存器中抑制时钟下降周期，同时抑制电路面积的增加，电流消耗的增加和成本增加，而不产生异常操作。 在基于提供给奇数级的两相时钟信号（GCK1，GCK3）和提供给奇数级的两相时钟信号（GCK2，GCK4）的四相时钟信号的移位寄存器（410）中， 到相位相互偏移90度的偶数级，当第一节点的电位处于高电平时，第一时钟（CKA）的电位作为扫描信号（GOUT）的电位出现 水平，在每个阶段。 在这种配置中，基于从前级输出的扫描信号的脉冲将每级中包括的第一节点的电位设置为高电平，并且基于扫描信号的脉冲将其设置为低电平 在有关阶段后从第三阶段输出。

公开(公告)号：US20130039455A1

公开(公告)日：2013-02-14

申请号：US13642714

申请日：2011-01-21

申请人： Satoshi Horiuchi ,  Masahiro Yoshida ,  Takaharu Yamada ,  Isao Ogasawara ,  Shinya Tanaka ,  Tetsuo Kikuchi

发明人： Satoshi Horiuchi ,  Masahiro Yoshida ,  Takaharu Yamada ,  Isao Ogasawara ,  Shinya Tanaka ,  Tetsuo Kikuchi

IPC分类号： G11C19/18

CPC分类号： G11C19/28 ,  G09G3/3677 ,  G09G2310/0286 ,  G11C19/184 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/7869

摘要： A shift register stage includes a first transistor having a capacitor electrode (CAPm) that faces, in a film thickness direction, at least one of source and drain electrodes (Tr4s and Tr4d) of the first transistor in a side opposite to a gate electrode (Tr4g) of the first transistor. One of (i) the capacitor electrode (CAPm) and (ii) the one of the source and drain electrodes (Tr4s and Tr4d) which faces the capacitor electrode (CAPm), is electrically connected to a control electrode of an output transistor of the shift register stage.

摘要翻译： 移位寄存器级包括具有电容器电极（CAPm）的第一晶体管，其在膜厚度方向上与第一晶体管的与栅电极相反的一侧中的至少一个源电极和漏电极（Tr4s和Tr4d） Tr4g）的第一晶体管。 （i）电容器电极（CAPm）和（ii）面对电容器电极（CAPm）的源极和漏极（Tr4s和Tr4d）中的一个电连接到输出晶体管的控制电极 移位寄存器阶段。

公开(公告)号：US20130038583A1

公开(公告)日：2013-02-14

申请号：US13642894

申请日：2011-01-28

申请人： Junya Shimada ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Chikao Yamasaki ,  Masahiro Yoshida ,  Satoshi Horiuchi ,  Isao Ogasawara

发明人： Junya Shimada ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Chikao Yamasaki ,  Masahiro Yoshida ,  Satoshi Horiuchi ,  Isao Ogasawara

IPC分类号： G11C19/00 ,  G06F3/038 ,  G09G3/36

CPC分类号： G11C19/28 ,  G09G3/3677

摘要： Provided is a shift register circuit which includes: first through N-th circuit sections (1a, 1b) (N is an integer equal to or larger than 2) in each of which a plurality of shift register stages (SR1, SR2, . . . , SRn) are connected in cascade; and supply wires (10b, 10c, 10e, 10f). Each of the first through N-th circuit sections (1a, 1b) receives drive signals (CKA1, CKA2, CKB1, CKB2) for driving the shift register stages (SR1, SR2, . . . , SRn) via supply wires (10b, 10c, 10e, 10f) exclusive for the each of the first through N-th circuit sections (1a, 1b).

摘要翻译： 提供一种移位寄存器电路，其包括：第一至第N电路部分（1a，1b）（N是等于或大于2的整数），其中每个电路部分中的多个移位寄存器级（SR1，SR2，...， 。，SRn）级联连接; 和电源线（10b，10c，10e，10f）。 第一至第N电路部分（1a，1b）中的每一个接收用于驱动移位寄存器级（SR1，SR2，...，SRn）的驱动信号（CKA1，CKA2，CKB1，CKB2） 10c，10e，10f）分别用于第一至第N电路部分（1a，1b）。

公开(公告)号：US20110291097A1

公开(公告)日：2011-12-01

申请号：US13138396

申请日：2009-11-05

申请人： Isao Ogasawara ,  Takaharu Yamada ,  Masahiro Yoshida ,  Satoshi Horiuchi ,  Shinya Tanaka ,  Tetsuo Kikuchi

发明人： Isao Ogasawara ,  Takaharu Yamada ,  Masahiro Yoshida ,  Satoshi Horiuchi ,  Shinya Tanaka ,  Tetsuo Kikuchi

IPC分类号： H01L33/16 ,  H01L29/786

CPC分类号： G02F1/136286 ,  G02F1/133345 ,  G02F1/1339 ,  G02F1/134336 ,  G02F1/1345 ,  G02F1/13452 ,  G02F1/13454 ,  H01L27/1222 ,  H01L27/124

摘要： An embodiment of the present invention provides a TFT array substrate, in which TFT elements and pixel electrodes being correspondingly connected with the TFT elements are arrayed in matrix on an insulating substrate, the TFT array substrate including: gate bus lines made from a first metal material; source bus lines made from a second metal material; pixel electrodes made from a third metal material; a clock wiring made from the first metal material; a branch wiring made from the second metal material; and a connection conductor made from the third metal material, the connection conductor connecting the clock wiring and the branch wiring at a connection part in a periphery area, the connection part having a branch-wiring via hole, which exposes the branch wiring which is covered with the connection conductor, and overlaps the clock wiring at least partly in a plane view.

摘要翻译： 本发明的实施例提供了一种TFT阵列基板，其中TFT元件和与TFT元件相对应的像素电极在矩阵上排列在绝缘基板上，该TFT阵列基板包括：由第一金属材料制成的栅极总线 ; 由第二金属材料制成的源总线; 由第三金属材料制成的像素电极; 由第一金属材料制成的时钟布线; 由第二金属材料制成的分支布线; 以及由第三金属材料制成的连接导体，连接导体在周边区域的连接部分连接时钟布线和分支布线，所述连接部分具有分支布线通孔，该布线通孔使被覆盖的分支布线 与连接导体，并且至少部分地在平面图中与时钟布线重叠。