公开(公告)号：US08928094B2

公开(公告)日：2015-01-06

申请号：US12875834

申请日：2010-09-03

申请人： Chun-Fai Cheng ,  Ka-Hing Fung ,  Shyh-Wei Wang ,  Chin-Te Su

发明人： Chun-Fai Cheng ,  Ka-Hing Fung ,  Shyh-Wei Wang ,  Chin-Te Su

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66

CPC分类号： H01L29/66545 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28525 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7848

摘要： The present disclosure provides a semiconductor device and methods of making wherein the semiconductor device has strained asymmetric source and drain regions. A method of fabricating the semiconductor device includes providing a substrate and forming a poly gate stack on the substrate. A dopant is implanted in the substrate at an implant angle ranging from about 10° to about 25° from perpendicular to the substrate. A spacer is formed adjacent the poly gate stack on the substrate. A source region and a drain region are etched in the substrate. A strained source layer and a strained drain layer are respectively deposited into the etched source and drain regions in the substrate, such that the source region and the drain region are asymmetric with respect to the poly gate stack. The poly gate stack is removed from the substrate and a high-k metal gate is formed using a gate-last process where the poly gate stack was removed.

摘要翻译： 本公开提供半导体器件及其制造方法，其中半导体器件具有应变的不对称源极和漏极区域。 制造半导体器件的方法包括提供衬底并在衬底上形成多晶硅叠层。 掺杂剂以垂直于衬底的约10°至约25°的注入角度注入衬底中。 邻近衬底上的多晶硅叠层形成间隔物。 源极区和漏极区被蚀刻在衬底中。 应变源极层和应变漏极层分别沉积在衬底中的蚀刻源极和漏极区域中，使得源极区域和漏极区域相对于多晶硅栅极叠层是不对称的。 多晶硅堆叠从衬底去除，并且使用去除多晶硅叠层的最后工艺形成高k金属栅极。

公开(公告)号：US08338909B2

公开(公告)日：2012-12-25

申请号：US12910638

申请日：2010-10-22

申请人： Ka-Hing Fung

发明人： Ka-Hing Fung

IPC分类号： H01L21/70 ,  H01L21/336

CPC分类号： H01L21/823481 ,  H01L21/76283 ,  H01L21/84

摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming a first isolation region in the semiconductor substrate; after the step of forming the first isolation region, forming a metal-oxide-semiconductor (MOS) device at a surface of the semiconductor substrate, wherein the step of forming the MOS device comprises forming a source/drain region; and after the step of forming the MOS device, forming a second isolation region in the semiconductor substrate.

摘要翻译： 形成集成电路结构的方法包括提供半导体衬底; 在所述半导体衬底中形成第一隔离区; 在形成第一隔离区域的步骤之后，在半导体衬底的表面形成金属氧化物半导体（MOS）器件，其中形成MOS器件的步骤包括形成源极/漏极区域; 并且在形成MOS器件的步骤之后，在半导体衬底中形成第二隔离区域。

公开(公告)号：US08153492B2

公开(公告)日：2012-04-10

申请号：US12869375

申请日：2010-08-26

申请人： Ka-Hing Fung

发明人： Ka-Hing Fung

IPC分类号： H01L21/336

CPC分类号： H01L29/4236 ,  H01L21/30608 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/11 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66621

摘要： Forming a high-κ/metal gate field effect transistor using a gate last process in which the channel region has a curved profile thus increasing the effective channel length improves the short channel effect. During the high-κ/metal gate process, after the sacrificial materials between the sidewall spacers are removed, the exposed semiconductor substrate surface at the bottom of the gate trench cavity is etched to form a curved recess. Subsequent deposition of high-κ gate dielectric layer and gate electrode metal into the gate trench cavity completes the high-κ/metal gate field effect transistor having a curved channel region that has a longer effective channel length.

摘要翻译： 使用栅极最后工艺形成高金属栅极场效应晶体管，其中沟道区域具有弯曲轮廓，从而增加有效沟道长度，改善了短沟道效应。 在高金属/金属栅极工艺期间，在去除侧壁间隔物之间​​的牺牲材料之后，蚀刻在栅极沟槽腔的底部的暴露的半导体衬底表面以形成弯曲凹槽。 随后的沉积 栅极电介质层和栅极电极金属进入栅极沟槽腔完成了具有较长有效沟道长度的弯曲沟道区的高金属栅极场效应晶体管。

公开(公告)号：US20120056276A1

公开(公告)日：2012-03-08

申请号：US12875834

申请日：2010-09-03

申请人： Chun-Fai Cheng ,  Ka-Hing Fung ,  Shyh-Wei Wang ,  Chin-Te Su

发明人： Chun-Fai Cheng ,  Ka-Hing Fung ,  Shyh-Wei Wang ,  Chin-Te Su

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28525 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7848

摘要： The present disclosure provides a semiconductor device and methods of making wherein the semiconductor device has strained asymmetric source and drain regions. A method of fabricating the semiconductor device includes providing a substrate and forming a poly gate stack on the substrate. A dopant is implanted in the substrate at an implant angle ranging from about 10° to about 25° from perpendicular to the substrate. A spacer is formed adjacent the poly gate stack on the substrate. A source region and a drain region are etched in the substrate. A strained source layer and a strained drain layer are respectively deposited into the etched source and drain regions in the substrate, such that the source region and the drain region are asymmetric with respect to the poly gate stack. The poly gate stack is removed from the substrate and a high-k metal gate is formed using a gate-last process where the poly gate stack was removed.

摘要翻译： 本公开提供半导体器件及其制造方法，其中半导体器件具有应变的不对称源极和漏极区域。 制造半导体器件的方法包括提供衬底并在衬底上形成多晶硅叠层。 掺杂剂以垂直于衬底的约10°至约25°的注入角度注入衬底中。 邻近衬底上的多晶硅叠层形成间隔物。 源极区和漏极区被蚀刻在衬底中。 应变源极层和应变漏极层分别沉积在衬底中的蚀刻源极和漏极区域中，使得源极区域和漏极区域相对于多晶硅栅极叠层是不对称的。 多晶硅堆叠从衬底去除，并且使用去除多晶硅叠层的最后工艺形成高k金属栅极。

公开(公告)号：US08053344B1

公开(公告)日：2011-11-08

申请号：US12886743

申请日：2010-09-21

申请人： Ka-Hing Fung ,  Wei-Yuan Lu ,  Han-Ting Tsai

发明人： Ka-Hing Fung ,  Wei-Yuan Lu ,  Han-Ting Tsai

IPC分类号： H01L29/00

CPC分类号： H01L21/2257 ,  H01L29/41783 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

摘要： A method of forming an integrated circuit includes forming a gate structure over a substrate. At least one silicon-containing layer is formed in source/drain (S/D) regions adjacent to sidewalls of the gate structure. An N-type doped silicon-containing layer is formed over the at least one silicon-containing layer. The N-type doped silicon-containing layer has an N-type dopant concentration higher than that of the at least one silicon-containing layer. The N-type doped silicon-containing layer is annealed so as to drive N-type dopants of the N-type doped silicon-containing layer to the S/D regions.

摘要翻译： 形成集成电路的方法包括在衬底上形成栅极结构。 在与栅极结构的侧壁相邻的源极/漏极（S / D）区域中形成至少一个含硅层。 在至少一个含硅层上形成N型掺杂含硅层。 N型掺杂含硅层的N型掺杂剂浓度高于至少一种含硅层。 对N型掺杂含硅层进行退火，以将N型掺杂含硅层的N型掺杂剂驱动到S / D区。

公开(公告)号：US20110031541A1

公开(公告)日：2011-02-10

申请号：US12910638

申请日：2010-10-22

申请人： Ka-Hing Fung

发明人： Ka-Hing Fung

IPC分类号： H01L29/78

CPC分类号： H01L21/823481 ,  H01L21/76283 ,  H01L21/84

摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming a first isolation region in the semiconductor substrate; after the step of forming the first isolation region, forming a metal-oxide-semiconductor (MOS) device at a surface of the semiconductor substrate, wherein the step of forming the MOS device comprises forming a source/drain region; and after the step of forming the MOS device, forming a second isolation region in the semiconductor substrate.

摘要翻译： 形成集成电路结构的方法包括提供半导体衬底; 在所述半导体衬底中形成第一隔离区; 在形成第一隔离区域的步骤之后，在半导体衬底的表面形成金属氧化物半导体（MOS）器件，其中形成MOS器件的步骤包括形成源极/漏极区域; 并且在形成MOS器件的步骤之后，在半导体衬底中形成第二隔离区域。

公开(公告)号：US07842577B2

公开(公告)日：2010-11-30

申请号：US12127646

申请日：2008-05-27

申请人： Ka-Hing Fung

发明人： Ka-Hing Fung

IPC分类号： H01L21/336

CPC分类号： H01L21/823481 ,  H01L21/76283 ,  H01L21/84

摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming a first isolation region in the semiconductor substrate; after the step of forming the first isolation region, forming a metal-oxide-semiconductor (MOS) device at a surface of the semiconductor substrate, wherein the step of forming the MOS device comprises forming a source/drain region; and after the step of forming the MOS device, forming a second isolation region in the semiconductor substrate.

摘要翻译： 形成集成电路结构的方法包括提供半导体衬底; 在所述半导体衬底中形成第一隔离区; 在形成第一隔离区域的步骤之后，在半导体衬底的表面形成金属氧化物半导体（MOS）器件，其中形成MOS器件的步骤包括形成源极/漏极区域; 并且在形成MOS器件的步骤之后，在半导体衬底中形成第二隔离区域。

公开(公告)号：US20090298248A1

公开(公告)日：2009-12-03

申请号：US12127646

申请日：2008-05-27

申请人： Ka-Hing Fung

发明人： Ka-Hing Fung

IPC分类号： H01L21/8234

CPC分类号： H01L21/823481 ,  H01L21/76283 ,  H01L21/84

摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming a first isolation region in the semiconductor substrate; after the step of forming the first isolation region, forming a metal-oxide-semiconductor (MOS) device at a surface of the semiconductor substrate, wherein the step of forming the MOS device comprises forming a source/drain region; and after the step of forming the MOS device, forming a second isolation region in the semiconductor substrate.

摘要翻译： 形成集成电路结构的方法包括提供半导体衬底; 在所述半导体衬底中形成第一隔离区; 在形成第一隔离区域的步骤之后，在半导体衬底的表面形成金属氧化物半导体（MOS）器件，其中形成MOS器件的步骤包括形成源极/漏极区域; 并且在形成MOS器件的步骤之后，在半导体衬底中形成第二隔离区域。

公开(公告)号：US20080283894A1

公开(公告)日：2008-11-20

申请号：US11803233

申请日：2007-05-14

申请人： Ka-Hing Fung ,  Carlos H. Diaz

发明人： Ka-Hing Fung ,  Carlos H. Diaz

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/7841 ,  H01L27/108 ,  H01L27/10802

摘要： A method for forming Z-RAM cells and the resulting semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate; a dielectric layer on the semiconductor substrate; an opening in the dielectric layer, wherein the semiconductor substrate is exposed through the opening; a semiconductor strip on the dielectric layer and adjacent the opening; a gate dielectric over a surface of the semiconductor strip; a gate electrode over the gate dielectric; and a source/drain region in the semiconductor strip and adjacent the gate electrode.

摘要翻译： 提供了一种形成Z-RAM单元的方法和所得到的半导体结构。 半导体结构包括半导体衬底; 半导体衬底上的介电层; 在所述介​​电层中的开口，其中所述半导体衬底通过所述开口暴露; 电介质层上的半导体条，邻近开口; 位于所述半导体条的表面上的栅介质; 位于栅极电介质上的栅电极; 以及半导体条带中的源极/漏极区域并且与栅电极相邻。