公开(公告)号：US08405160B2

公开(公告)日：2013-03-26

申请号：US12787972

申请日：2010-05-26

Applicant: Chun-Fai Cheng ,  Fung Ka Hing ,  Ming-Huan Tsai ,  Chun-Feng Nieh ,  Yimin Huang ,  Han-Ting Tsai ,  Haiting Wang

Inventor： Chun-Fai Cheng ,  Fung Ka Hing ,  Ming-Huan Tsai ,  Chun-Feng Nieh ,  Yimin Huang ,  Han-Ting Tsai ,  Haiting Wang

IPC: H01L27/088 ,  H01L21/8238

CPC classification number: H01L29/7848 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30608 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. The semiconductor device includes first and second regions that are disposed in the substrate. The first and second regions have a silicon compound material. The semiconductor device includes first and second source/drain structures that are partially disposed in the first and second regions, respectively. The semiconductor device includes a first gate that is disposed over the substrate. The first gate has a first proximity to the first region. The semiconductor device includes a second gate that is disposed over the substrate. The second gate has a second proximity to the second region. The second proximity is different from the first proximity. The first source/drain structure and the first gate are portions of a first transistor, and the second source/drain structure and the second gate are portions of a second transistor.

Abstract translation: 本发明提供一种半导体器件。 半导体器件包括硅衬底。 半导体器件包括设置在衬底中的第一和第二区域。 第一和第二区域具有硅化合物材料。 半导体器件包括分别部分地设置在第一和第二区域中的第一和第二源极/漏极结构。 半导体器件包括设置在衬底上的第一栅极。 第一个门第一个靠近第一个地区。 半导体器件包括设置在衬底上的第二栅极。 第二个门第二个靠近第二个区域。 第二接近度与第一接近度不同。 第一源极/漏极结构和第一栅极是第一晶体管的部分，并且第二源极/漏极结构和第二栅极是第二晶体管的部分。

公开(公告)号：US20130026579A1

公开(公告)日：2013-01-31

申请号：US13191297

申请日：2011-07-26

Applicant: Wei-Yuan Lu ,  Kuan-Chung Chen ,  Chun-Fai Cheng

Inventor： Wei-Yuan Lu ,  Kuan-Chung Chen ,  Chun-Fai Cheng

IPC: H01L27/11 ,  H01L21/8239

CPC classification number: H01L27/11 ,  H01L21/28176 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7827

Abstract: A method for manufacturing a semiconductor device includes forming a first dummy gate on a substrate, performing a doping process to the substrate, thereby forming a source and a drain at sides of the first dummy gate, performing a first high temperature annealing to activate the source and drain, forming an inter-layer dielectric (ILD) material on the substrate, removing the first dummy gate to create an ILD trench, forming a first high-k dielectric layer within the ILD trench, forming a first dummy cap portion within the ILD trench over the first high-k dielectric layer, performing a second high-temperature annealing to reduce defects in the first high-k dielectric layer, and thereafter, replacing the first dummy cap portion with a first metal gate electrode.

Abstract translation: 一种制造半导体器件的方法包括：在衬底上形成第一虚拟栅极，对衬底进行掺杂处理，从而在第一虚拟栅极的侧面形成源极和漏极，执行第一高温退火以激活源极 和漏极，在所述衬底上形成层间电介质（ILD）材料，去除所述第一虚拟栅极以产生ILD沟槽，在所述ILD沟槽内形成第一高k电介质层，在所述ILD沟槽内形成第一虚拟帽部分 在第一高k电介质层上的沟槽，进行第二高温退火以减少第一高k电介质层中的缺陷，然后用第一金属栅极电极代替第一虚设帽部。

公开(公告)号：US20120273847A1

公开(公告)日：2012-11-01

申请号：US13543943

申请日：2012-07-09

Applicant: Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

Inventor： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

IPC: H01L27/085

CPC classification number: H01L21/823807 ,  H01L21/02433 ,  H01L21/02639 ,  H01L21/823814 ,  H01L29/7848

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit devices. An exemplary integrated circuit device achieved by the method has a surface proximity of about 1 nm to about 3 nm and a tip depth of about 5 nm to about 10 nm. The integrated circuit device having such surface proximity and tip depth includes an epi source feature and an epi drain feature defined by a first facet and a second facet of a substrate in a first direction, such as a {111} crystallographic plane of the substrate, and a third facet of the substrate in a second direction, such as a { 100} crystallographic plane of the substrate.

Abstract translation: 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 通过该方法实现的示例性集成电路器件具有约1nm至约3nm的表面接近度和约5nm至约10nm的尖端深度。 具有这种表面接近度和尖端深度的集成电路器件包括由第一方向（例如衬底的{111}晶体平面）的第一方向上的第一面和第二小面限定的外延源特征和外延漏极特征， 以及在第二方向上的衬底的第三面，例如衬底的{100}晶面。

公开(公告)号：US20110312145A1

公开(公告)日：2011-12-22

申请号：US12816519

申请日：2010-06-16

Applicant: Ming-Huan Tsai ,  Chun-Fai Cheng ,  Hui Ouyang ,  Yuan-Hung Chiu ,  Yen-Ming Chen

Inventor： Ming-Huan Tsai ,  Chun-Fai Cheng ,  Hui Ouyang ,  Yuan-Hung Chiu ,  Yen-Ming Chen

IPC: H01L21/336

CPC classification number: H01L29/66515 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.

Abstract translation: 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。 掺杂区域注入与LDD区域相反的掺杂剂类型。

公开(公告)号：US20110254105A1

公开(公告)日：2011-10-20

申请号：US12761949

申请日：2010-04-16

Applicant: Chun-Fai Cheng ,  Ka-Hing Fung ,  Han-Ting Tsai ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Hsueh-Chang Sung ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

Inventor： Chun-Fai Cheng ,  Ka-Hing Fung ,  Han-Ting Tsai ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Hsueh-Chang Sung ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/28518 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes.

Abstract translation: 提供了具有应变通道的半导体器件及其制造方法。 半导体器件具有形成在通道凹槽上的栅电极。 形成在栅电极的相对侧上的第一凹部和第二凹部填充有应力诱导材料。 应力诱导材料延伸到其中源极/漏极延伸部与栅电极的边缘重叠的区域中。 在一个实施例中，通道凹槽和/或第一和第二凹部的侧壁可以沿{111}面平面。

公开(公告)号：US20110223752A1

公开(公告)日：2011-09-15

申请号：US12720075

申请日：2010-03-09

Applicant: Fung Ka HING ,  Haiting WANG ,  Han-Ting TSAI ,  Chun-Fai CHENG ,  Wei-Yuan LU ,  Hsien-Ching LO ,  Kuan-Chung CHEN

Inventor： Fung Ka HING ,  Haiting WANG ,  Han-Ting TSAI ,  Chun-Fai CHENG ,  Wei-Yuan LU ,  Hsien-Ching LO ,  Kuan-Chung CHEN

IPC: H01L21/28

CPC classification number: H01L29/7833 ,  H01L21/76834 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/7836

Abstract: The present disclosure discloses an exemplary method for fabricating a gate structure comprising depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a sacrificial layer; surrounding the sacrificial layer with a nitrogen-containing dielectric layer; surrounding the nitrogen-containing dielectric layer with an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer; removing the sacrificial layer to form an opening in the nitrogen-containing dielectric layer; and depositing a gate dielectric; and depositing a gate electrode.

Abstract translation: 本公开公开了一种用于制造栅极结构的示例性方法，其包括在衬底上沉积和图案化虚拟氧化物层和伪栅极电极层; 围绕所述虚拟氧化物层和所述伪栅极电极层，具有牺牲层; 用含氮介电层围绕牺牲层; 用层间介质层包围含氮介电层; 去除所述伪栅电极层; 去除虚拟氧化物层; 去除所述牺牲层以在所述含氮介电层中形成开口; 并沉积栅极电介质; 并沉积栅电极。

公开(公告)号：US20110193167A1

公开(公告)日：2011-08-11

申请号：US12704367

申请日：2010-02-11

Applicant: Ka-Hing Fung ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo

Inventor： Ka-Hing Fung ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo

IPC: H01L27/12 ,  H01L27/105

CPC classification number: H01L27/1203 ,  H01L21/26506 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

Abstract: An integrated circuit structure includes a semiconductor substrate including an active region. A first shallow trench isolation (STI) region adjoins a first side of the active region. A gate electrode of a MOS device is over the active region and the first STI region. A source/drain stressor region of the MOS device includes a portion in the semiconductor substrate and adjacent the gate electrode. A trench is formed in the semiconductor substrate and adjoining a second side of the active region. The trench has a bottom no lower than a bottom of the source/drain region. An inter-layer dielectric (ILD) extends from over the gate electrode to inside the trench, wherein a portion of the ILD in the trench forms a second STI region. The second STI region and the source/drain stressor region are separated from each other by, and adjoining, a portion of the semiconductor substrate.

Abstract translation: 集成电路结构包括包括有源区的半导体衬底。 第一浅沟槽隔离（STI）区域邻接有源区域的第一侧。 MOS器件的栅电极在有源区和第一STI区之上。 MOS器件的源极/漏极应力区域包括半导体衬底中的与栅电极相邻的部分。 在半导体衬底中形成沟槽，并与有源区域的第二面相邻。 沟槽的底部不低于源极/漏极区域的底部。 层间电介质（ILD）从栅极电极延伸到沟槽内部，其中沟槽中的ILD的一部分形成第二STI区域。 第二STI区域和源极/漏极应力区域彼此分离并邻接半导体衬底的一部分。

公开(公告)号：US08872228B2

公开(公告)日：2014-10-28

申请号：US13469526

申请日：2012-05-11

Applicant: Chun-Fai Cheng ,  Bwo-Ning Chen ,  Chin-Te Su ,  Huang-Sheng Ho

Inventor： Chun-Fai Cheng ,  Bwo-Ning Chen ,  Chin-Te Su ,  Huang-Sheng Ho

IPC: H01L29/66 ,  H01L21/336 ,  H01L21/8234

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for controlling IC device strain and the devices thereby formed are disclosed. An exemplary embodiment includes receiving an IC device substrate having a device region corresponding to an IC device. An implantation process is performed on the device region forming an amorphous region within the device region. The IC device substrate is recessed to define a source/drain recess in the device region having a profile determined by the amorphous structure of the amorphous region. A source/drain epitaxy is then performed to form a source/drain structure within the source/drain recess.

Abstract translation: 公开了一种用于控制IC器件应变的方法和由此形成的器件。 示例性实施例包括接收具有对应于IC器件的器件区域的IC器件衬底。 在器件区域内形成非晶区域的器件区域上进行注入工艺。 IC器件衬底被凹入以在器件区域中限定具有由非晶区域的无定形结构确定的分布的源极/漏极凹部。 然后进行源极/漏极外延，以在源极/漏极凹部内形成源极/漏极结构。

公开(公告)号：US20140210874A1

公开(公告)日：2014-07-31

申请号：US14071169

申请日：2013-11-04

Applicant: CHUN-FAI CHENG

Inventor： CHUN-FAI CHENG

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G3/30 ,  G09G3/3614 ,  G09G2310/0259 ,  G09G2310/027 ,  G09G2320/0276

Abstract: A circuit and method of driving a display panel requiring gray scale control wherein the voltage applied to a row of pixels is equal to the sum of voltages of opposite sign with respect to ground applied respectively to the row electrode and column electrodes whose intersection with the row defines the pixels. Gray scale is realized through modulation of the voltage applied to the column electrodes. Typically for video application, 256 individual gray levels are required corresponding to luminance levels ranging from zero (no emissive luminance) to full luminance. The required luminance for each gray level is not a linear function of the gray level number but rather corresponds to an approximate quadratic function of this number. The present invention facilitates generation of luminance values for each gray level that approximates this functional dependence (i.e. Gamma corrected) with a non-linear voltage ramp terminated by a digital clock having 256 (8 bit) resolution. The voltage at the ramp termination is held at a constant value and fed to the output buffer of the gray scale drivers for the display columns.

Abstract translation: 驱动需要灰度控制的显示面板的电路和方法，其中施加到一行像素的电压等于分别施加到相对于地面的相对符号的电压之和，与行电极和列电极的与行的交点相加 定义像素。 通过调制施加到列电极的​​电压来实现灰度级。 通常对于视频应用，需要对应于从零（无发光亮度）到全亮度的亮度级别需要256个单独的灰度级。 每个灰度级的所需亮度不是灰度级数的线性函数，而是对应于该数的近似二次函数。 本发明有助于以由具有256（8位）分辨率的数字时钟终止的非线性电压斜坡来生成近似该功能依赖性（即，伽马校正）的每个灰度级的亮度值。 斜坡端接电压保持恒定值，并送到显示列的灰度级驱动器的输出缓冲器。

公开(公告)号：US08680625B2

公开(公告)日：2014-03-25

申请号：US12905579

申请日：2010-10-15

Applicant: Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang ,  Ming-Huan Tsai ,  Hsueh-Chang Sung ,  Chun-Fai Cheng

Inventor： Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang ,  Ming-Huan Tsai ,  Hsueh-Chang Sung ,  Chun-Fai Cheng

IPC: H01L27/088

CPC classification number: H01L29/165 ,  H01L21/28123 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: An exemplary semiconductor device is described, which includes a semiconductor substrate having an active region and an isolation region. The active region has a first edge which interfaces with the isolation region. A gate structure formed on the semiconductor substrate. A spacer element abuts the gate structure and overlies the first edge. In an embodiment, the isolation region is an STI structure. An epitaxy region may be formed adjacent the spacer. In embodiments, this epitaxy region is facet-free.

Abstract translation: 描述了一种示例性的半导体器件，其包括具有有源区和隔离区的半导体衬底。 有源区域具有与隔离区域相接合的第一边缘。 形成在半导体衬底上的栅极结构。 间隔元件邻接栅极结构并覆盖在第一边缘上。 在一个实施例中，隔离区域是STI结构。 可以在间隔物附近形成外延区域。 在实施例中，该外延区域是无面的。