公开(公告)号：US20230141572A1

公开(公告)日：2023-05-11

申请号：US18092908

申请日：2023-01-03

Applicant: Silicon Motion, Inc.

Inventor： Tien-Hsing Yao ,  Chun-Cheng Lee ,  Sheng-I Hsu

IPC: H03K21/02 ,  H03K21/10 ,  G06F1/3234 ,  H03K5/00 ,  H03K21/40

CPC classification number: H03K21/026 ,  H03K21/10 ,  G06F1/3275 ,  H03K5/00006 ,  H03K21/406

Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

公开(公告)号：US11323122B2

公开(公告)日：2022-05-03

申请号：US17331577

申请日：2021-05-26

Applicant: Silicon Motion, Inc.

Inventor： Tien-Hsing Yao ,  Chun-Cheng Lee ,  Sheng-I Hsu

IPC: H03K21/02 ,  H03K21/08 ,  H03K5/00 ,  H03K21/40 ,  H03K21/10 ,  G06F1/3234

Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values. The control signal generator is configured to generate a control signal based on an input clock signal and values in the at least a portion of the registers, wherein the control generator sequentially generates the control signal during each cycle of the input clock signal. The clock gating circuit is configured to refer to the control signal to mask or not mask the input clock signal to generate an output clock signal.

公开(公告)号：US11188265B2

公开(公告)日：2021-11-30

申请号：US16852526

申请日：2020-04-19

Applicant: Silicon Motion, Inc.

Inventor： Sheng-I Hsu ,  Ching-Chin Chang

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/10

Abstract: A method for performing storage space management, an associated data storage device, and a controller thereof are provided. The method includes: receiving an identify controller command from a host device; in response to the identify controller command, returning a reply to the host device to indicate that a plurality of logical block address (LBA) formats are supported, where the plurality of LBA formats are related to access of a non-volatile (NV) memory, and the plurality of LBA formats include a first LBA format and a second LBA format; receiving a first namespace (NS) management command from the host device; in response to the first NS management command, establishing a first NS adopting the first LBA format; receiving a second NS management command from the host device; and in response to the second NS management command, establishing a second NS adopting the second LBA format.

公开(公告)号：US10671322B1

公开(公告)日：2020-06-02

申请号：US16271899

申请日：2019-02-11

Applicant: Silicon Motion Inc.

Inventor： Sheng-I Hsu ,  Ching-Chin Chang

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/10

Abstract: A method for performing storage space management, an associated data storage device, and a controller thereof are provided. The method includes: receiving an identify controller command from a host device; in response to the identify controller command, returning a reply to the host device to indicate that a plurality of logical block address (LBA) formats are supported, where the plurality of LBA formats are related to access of a non-volatile (NV) memory, and the plurality of LBA formats include a first LBA format and a second LBA format; receiving a first namespace (NS) management command from the host device; in response to the first NS management command, establishing a first NS adopting the first LBA format; receiving a second NS management command from the host device; and in response to the second NS management command, establishing a second NS adopting the second LBA format.

公开(公告)号：US20180341545A1

公开(公告)日：2018-11-29

申请号：US16053815

申请日：2018-08-03

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Sheng-I Hsu

IPC: G06F11/10 ,  G06F12/02 ,  H03M13/29 ,  H03M13/09 ,  H03M13/13

Abstract: A data storage system includes a processing circuit, a lookup table (LUT), and a decoding circuit. The processing circuit is arranged to receive a first logical block address (LBA) from a host. The LUT is arranged to store a storage address mapping to the first LBA. The decoding circuit is arranged to utilize the storage address to read storage data from a storing circuit, and decode a first data sector in the storage data according to an error checking and correcting code in the storage data, and the first data sector at least comprises a second LBA.

公开(公告)号：US20180260151A1

公开(公告)日：2018-09-13

申请号：US15848973

申请日：2017-12-20

Applicant: Silicon Motion, Inc.

Inventor： Sheng-I Hsu

IPC: G06F3/06

CPC classification number: G06F3/0623 ,  G06F3/0638 ,  G06F3/0673 ,  G06F21/6218

Abstract: A security mechanism for a data storage device. The data storage device includes a nonvolatile memory and a control unit. The control unit uses a dynamic random access memory at a host side with an encryption mechanism when operating the nonvolatile memory. The control unit protects keys of the encryption mechanism within the data storage device to isolate the keys from the host.

公开(公告)号：US09411686B2

公开(公告)日：2016-08-09

申请号：US14331591

申请日：2014-07-15

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Yang-Chih Shen ,  Sheng-I Hsu

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/108 ,  G06F11/1012 ,  G06F2211/109

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. After all messages within a RAID (Redundant Array of Independent Disk) group are programmed, it is determined whether a vertical ECC (Error Correction Code) within the RAID group has been generated. The processing unit directs a DMA (Direct Memory Access) controller to obtain the vertical ECC from a DRAM (Dynamic Random Access Memory) and store the vertical ECC to a buffer when the vertical ECC within the RAID group has been generated, thereby enabling the vertical ECC to be programmed to the storage unit.

Abstract translation: 用于访问由处理单元执行的闪速存储器的存储单元的方法的实施例至少包括以下步骤。 在RAID（独立磁盘冗余阵列）组中的所有消息被编程之后，确定是否已经生成RAID组内的垂直ECC（纠错码）。 处理单元引导DMA（直接存储器访问）控制器从DRAM（动态随机存取存储器）获得垂直ECC，并且当生成RAID组内的垂直ECC时，将垂直ECC存储到缓冲器，从而使垂直 ECC被编程到存储单元。

公开(公告)号：US20150058662A1

公开(公告)日：2015-02-26

申请号：US14331575

申请日：2014-07-15

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Yang-Chih Shen ,  Sheng-I Hsu

IPC: G06F11/10 ,  G06F12/02 ,  G11C29/52

CPC classification number: G06F11/108 ,  G06F3/06 ,  G06F12/0246 ,  G11C2029/0411

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by an arbiter, includes at least the following steps. After transmitting data to first storage units each connected to one of storage-unit access interfaces in a first batch, the arbiter issues a data write command to each first storage unit, thereby enabling each first storage unit to start a physical data programming. During the physical data programming of each first storage unit, data is transmitted to second storage units each connected to one of the storage-unit access interfaces in a second batch.

Abstract translation: 用于访问由仲裁器执行的闪速存储器的存储单元的方法的实施例至少包括以下步骤。 在第一批中将数据发送到连接到存储单元访问接口中的一个的第一存储单元之后，仲裁器向每个第一存储单元发出数据写入命令，从而使得每个第一存储单元能够启动物理数据编程。 在每个第一存储单元的物理数据编程期间，数据被发送到第二存储单元，每个存储单元在第二批中连接到一个存储单元访问接口。