公开(公告)号：US4423371A

公开(公告)日：1983-12-27

申请号：US299264

申请日：1981-09-03

Applicant: Stephen D. Senturia ,  Steven L. Garverick

Inventor： Stephen D. Senturia ,  Steven L. Garverick

IPC: G01N27/22 ,  G01N33/44 ,  G01R27/02

CPC classification number: G01N33/442 ,  G01N27/221 ,  G01R27/02

Abstract: An impedance measuring apparatus having a measuring transistor with its gate electrode adapted to form a two electrode, interdigitated capacitor with the material to be measured forming the dielectric, a second reference transistor connected in differential configuration to the measuring transistor so that their drain currents are constrained to be equal, a time-varying voltage generator connected to one electrode of the interdigitated capacitor and a gain-phase meter connected to the gate of the reference transistor.

Abstract translation: 一种具有测量晶体管的阻抗测量装置，其栅电极适于与被测材料形成介质的两个电极，叉指电容器，以差分配置连接到测量晶体管的第二参考晶体管，使得它们的漏极电流受到约束 相等的是连接到交错电容器的一个电极的时变电压发生器和连接到参考晶体管的栅极的增益相位计。

公开(公告)号：US4316140A

公开(公告)日：1982-02-16

申请号：US76037

申请日：1979-09-17

Applicant: Stephen D. Senturia

Inventor： Stephen D. Senturia

IPC: G01N27/414 ,  H01L29/43 ,  G01N27/00 ,  H01L29/78 ,  H01L29/84

CPC classification number: H01L29/435 ,  G01N27/4148

Abstract: A charge-flow transistor having a source region and a drain region in a semiconductor substrate, a gate insulator and a gapped gate electrode with a gap material having some electrical conductance disposed in the gap thereof.

Abstract translation: 具有半导体衬底中的源极区和漏极区的电荷流量晶体管，栅极绝缘体和间隙材料具有间隙材料的间隙栅电极设置在其间隙中。

公开(公告)号：US4209796A

公开(公告)日：1980-06-24

申请号：US853059

申请日：1977-11-21

Applicant: Stephen D. Senturia

Inventor： Stephen D. Senturia

IPC: G01N27/00 ,  G01N27/414 ,  H01L21/765 ,  H01L21/8247 ,  H01L27/088 ,  H01L27/105 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/43 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC classification number: G01N27/414 ,  H01L21/765 ,  H01L27/088 ,  H01L27/105 ,  H01L29/0638 ,  H01L29/41725 ,  H01L29/4232 ,  H01L29/435 ,  H01L29/78 ,  H01L29/7831

Abstract: A charge-flow transistor having a source region and a drain region in a semiconductor substrate, a gate insulator, and a gapped gate electrode with a thin-film material having some electrical conductance disposed in the gap thereof. Metallization patterns are provided to reduce the detrimental effect of parasitic currents that appear within the transistor. There is disclosed also a plurality of such transistors in a single die with metallization to reduce any effect of parasitic currents between the transistors of the plurality.

Abstract translation: 具有在半导体衬底中的源极区和漏极区的电荷流动晶体管，栅极绝缘体和具有设置在其间隙中的具有一些导电性的薄膜材料的间隙栅电极。 提供金属化模式以减少出现在晶体管内的寄生电流的有害影响。 在具有金属化的单个管芯中还公开了多个这样的晶体管，以减少多个晶体管之间的寄生电流的任何影响。