利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

60 条记录 (耗时 0.021 秒)

    Semiconductor device protection circuit
    31.
    发明授权
    Semiconductor device protection circuit 失效
    半导体器件保护电路

    公开(公告)号：US5119265A

    公开(公告)日：1992-06-02

    申请号：US502716

    申请日：1990-04-02

    申请人： John R. Qualich ,  Stephen P. Robb ,  John M. Pigott

    发明人： John R. Qualich ,  Stephen P. Robb ,  John M. Pigott

    IPC分类号： H03K17/00 ,  H03K17/08 ,  H03K17/082 ,  H03K17/16

    CPC分类号： H03K17/08 ,  H03K17/0822 ,  H03K17/165 ,  H03K2017/0806 ,  H03K2217/0036 ,  Y10S323/907

    摘要： FET protection circuit (10; 100) senses the temperature of a FET (11) and, via a control circuit (24), increases FET conduction in response to sensed FET temperature exceeding a high temperature threshold (160.degree. C.) close to the maximum rated junction temperature (175.degree. C.) of the FET. This allows the FET to survive excessive drain-to-source voltages which occur during load dump conditions even when load dump is sensed by a zener diode (26) which initially turns on the FET. During load dump after a zener diode (26) turns on the FET, in response to sensing excessive FET temperature the FET is turned in harder so as to reduce the drain-to-source voltage (V.sub.DS) and minimize power dissipation during load dump thereby protecting the FET. Normal overcurrent and maximum temperture turn off circuitry (44, 33, 60-63) is effectively overridden by high temperature threshold turn-on circuitry (50). Preferably, a majority of the control circuit (24) is provided on an integrated circuit, but an external resistor (31) allows effective adjustment of two temperature thresholds (150.degree. C., 160.degree. C.) above which control signals provided to the FET will be modified.

    摘要翻译： FET保护电路（10; 100）感测FET（11）的温度，并且经由控制电路（24）响应于感测到的FET温度超过接近于最高温度阈值（160℃）的FET温度而增加FET导通 FET的最大额定结温（175℃）。 这允许FET在负载突降条件期间发生的过度的漏极 - 源极电压存活，即使当最初导通FET的齐纳二极管（26）感测到负载突降时。 在齐纳二极管（26）接通FET之后的负载突降期间，响应于感测到过高的FET温度，FET变得更硬，以便减少漏极 - 源极电压（VDS）并且最小化负载突降期间的功率耗散 保护FET。 正常过电流和最大温度关闭电路（44,33,60-63）被高温阈值导通电路（50）有效地覆盖。 优选地，控制电路（24）的大部分设置在集成电路上，但是外部电阻器（31）允许有效地调整两个温度阈值（150℃，160℃） FET将被修改。

    Avalanche stress protected semiconductor device having variable input impedance
    32.
    发明授权
    Avalanche stress protected semiconductor device having variable input impedance 失效
    具有可变输入阻抗的雪崩应力保护半导体器件

    公开(公告)号：US5115369A

    公开(公告)日：1992-05-19

    申请号：US637719

    申请日：1991-01-07

    申请人： Stephen P. Robb ,  John P. Phipps ,  Michael D. Gadberry

    发明人： Stephen P. Robb ,  John P. Phipps ,  Michael D. Gadberry

    IPC分类号： H01L27/02

    CPC分类号： H01L27/0251

    摘要： A power transistor having a control electrode which is coupled to a polysilicon JFET transistor is provided. In particular, a power MOSFET device having a polysilicon gate is formed and a JFET transistor is formed in the same polysilicon layer which forms the gate of the power MOSFET. A drain of the JFET forms an input terminal for the power MOSFET and a source of the JFET is coupled to the gate of the power MOSFET. A gate of the JFET is coupled to a gate-drain diode clamp so that when the gate-drain diode clamp is activated a portion of the current which is used to turn on the power MOSFET is channeled to the gate of the JFET and increases the drain-to-source series resistance of the JFET. The resistance of the JFET is low during normal operation and increases only when the gate-drain clamp is activated thus provides a high resistance during avalanche stress protection and a low resistance during normal operation.

    摘要翻译： 提供了具有耦合到多晶硅JFET晶体管的控制电极的功率晶体管。 特别地，形成具有多晶硅栅极的功率MOSFET器件，并且在形成功率MOSFET的栅极的同一多晶硅层中形成JFET晶体管。 JFET的漏极形成用于功率MOSFET的输入端子，并且JFET的源极耦合到功率MOSFET的栅极。 JFET的栅极耦合到栅极 - 漏极二极管钳位，使得当栅极 - 漏极二极管钳位被激活时，用于接通功率MOSFET的电流的一部分被引导到JFET的栅极，并且增加 漏极到源极串联电阻的JFET。 在正常工作期间，JFET的电阻很低，只有当栅极 - 漏极钳位被激活时才增加，因此在雪崩应力保护期间提供高电阻，并在正常工作期间提供低电阻。

    Avalanche stress protected semiconductor device having variable input impedance
    33.
    发明授权
    Avalanche stress protected semiconductor device having variable input impedance 失效
    具有可变输入阻抗的雪崩应力保护半导体器件

    公开(公告)号：US5005061A

    公开(公告)日：1991-04-02

    申请号：US474889

    申请日：1990-02-05

    申请人： Stephen P. Robb ,  John P. Phipps ,  Michael D. Gadberry

    发明人： Stephen P. Robb ,  John P. Phipps ,  Michael D. Gadberry

    IPC分类号： H01L27/02

    CPC分类号： H01L27/0251

    摘要： A power transistor having a control electrode which is coupled to a polysilicon JFET transistor is provided. In particular, a power MOSFET device having a polysilicon gate is formed and a JFET transistor is formed in the same polysilicon layer which forms the gate of the power MOSFET. A drain of the JFET forms an input terminal for the power MOSFET and a source of the JFET is coupled to the gate of the power MOSFET. A gate of the JFET is copupled to a gate-drain diode clamp so that when the gate-drain diode clamp is activated a portion of the current which is used to turn on the power MOSFET is channeled to the gate of the JFET and increases the drain-to-source series resistance of the JFET. The resistance of the JFET is low during normal operation and increases only when the gate-drain clamp is activated thus provides a high resistance during avalanche stress protection and a low resistance during normal operation.

    摘要翻译： 提供了具有耦合到多晶硅JFET晶体管的控制电极的功率晶体管。 特别地，形成具有多晶硅栅极的功率MOSFET器件，并且在形成功率MOSFET的栅极的同一多晶硅层中形成JFET晶体管。 JFET的漏极形成用于功率MOSFET的输入端子，并且JFET的源极耦合到功率MOSFET的栅极。 JFET的栅极被耦合到栅 - 漏二极管钳位，使得当栅极 - 漏极二极管钳位被激活时，用于接通功率MOSFET的电流的一部分被引导到JFET的栅极，并且增加 漏极到源极串联电阻的JFET。 在正常工作期间，JFET的电阻很低，只有当栅极 - 漏极钳位被激活时才增加，因此在雪崩应力保护期间提供高电阻，并在正常工作期间提供低电阻。

    LED control circuit and method therefor
    36.
    发明授权
    LED control circuit and method therefor 有权
    LED控制电路及其方法

    公开(公告)号：US07839099B2

    公开(公告)日：2010-11-23

    申请号：US11399523

    申请日：2006-04-07

    申请人： Alan R. Ball ,  Stephen P. Robb

    发明人： Alan R. Ball ,  Stephen P. Robb

    IPC分类号： G05F1/00

    CPC分类号： H05B33/0851

    摘要： In one embodiment, an LED control circuit is configured control a current through an LED responsively to a value that is proportional to a control signal for values of the control signal that are less than a threshold value of the control signal and to control the current to a value that is proportional to the threshold value for values of the control signal that are greater than the threshold value.

    摘要翻译： 在一个实施例中，LED控制电路被配置为响应于与控制信号成比例的控制信号的值响应于控制信号的值而控制电流，所述值控制信号的值小于控制信号的阈值，并且控制电流 与控制信号的阈值成比例的值大于阈值的值。

    Method of forming an in-rush limiter and structure therefor
    38.
    发明授权
    Method of forming an in-rush limiter and structure therefor 有权
    形成入侵限制器及其结构的方法

    公开(公告)号：US07508641B2

    公开(公告)日：2009-03-24

    申请号：US11144417

    申请日：2005-06-06

    申请人： Alan R. Ball ,  Stephen P. Robb

    发明人： Alan R. Ball ,  Stephen P. Robb

    IPC分类号： H02H3/00

    CPC分类号： G05F1/573

    摘要： In one embodiment, an in-rush limiter is configured to control an output voltage to increase at a rate that is independent of the load that is powered by the in-rush limiter.

    摘要翻译： 在一个实施例中，浪涌限制器被配置为控制输出电压以独立于通过入侵限制器供电的负载的速率增加。

    Semiconductor device and method of making
    40.
    发明授权
    Semiconductor device and method of making 失效
    半导体器件及其制造方法

    公开(公告)号：US06507070B1

    公开(公告)日：2003-01-14

    申请号：US08755926

    申请日：1996-11-25

    申请人： Zheng Shen ,  Stephen P. Robb ,  Chang Su Mitter

    发明人： Zheng Shen ,  Stephen P. Robb ,  Chang Su Mitter

    IPC分类号： H01L2976

    CPC分类号： H01L29/0847 ,  H01L29/167 ,  H01L29/4175 ,  H01L29/7835

    摘要： A semiconductor device (10) is formed that is bi-lateral and has a voltage blocking capability that is well suited to applications involving portable electronics. The semiconductor device has an epitaxial layer (14) that is formed on a semiconductor substrate (11). A doped region (24) is formed that extends from a top surface (16) of the epitaxial layer (14) to the underlying semiconductor substrate (11). The semiconductor device (10) has a source region (31) that is separated from the doped region (24) to provide a channel region (29). The channel region (29) is modulated by a gate structure (20) to determine if a current flow should be allowed through semiconductor device (10) or if semiconductor device (10) is to provide voltage blocking capability.

    摘要翻译： 半导体器件（10）形成为双向的并且具有非常适合涉及便携式电子设备的应用的电压阻挡能力。 半导体器件具有形成在半导体衬底（11）上的外延层（14）。 形成从外延层（14）的顶表面（16）延伸到下面的半导体衬底（11）的掺杂区域（24）。 半导体器件（10）具有与掺杂区域（24）分离以提供沟道区域（29）的源极区域（31）。 沟道区域（29）由栅极结构（20）调制以确定是否允许电流通过半导体器件（10），或者半导体器件（10）是否提供电压阻挡能力。