公开(公告)号：US5266831A

公开(公告)日：1993-11-30

申请号：US790795

申请日：1991-11-12

申请人： John P. Phipps ,  Stephen P. Robb

发明人： John P. Phipps ,  Stephen P. Robb

IPC分类号： H01L27/02 ,  H01L29/06 ,  H01L21/04 ,  H01L23/60

CPC分类号： H01L29/7808 ,  H01L27/0255 ,  H01L29/0619 ,  H01L29/0696 ,  H01L2924/0002

摘要： A semiconductor structure having an edge termination feature wherein at least one guard ring is disposed in a substrate between a main device portion and the edge of the substrate. A dielectric layer is then disposed on the substrate and a plurality of diodes are disposed on the dielectric layer above the at least one guard ring. The at least one guard ring and the diodes are electrically coupled so that the potential of the guard rings may be fixed by the diodes and leakage is greatly reduced.

摘要翻译： 一种具有边缘终止特征的半导体结构，其中至少一个保护环设置在主要器件部分和衬底的边缘之间的衬底中。 然后将介电层设置在基板上，并且多个二极管设置在至少一个保护环上方的电介质层上。 至少一个保护环和二极管被电耦合，使得保护环的电位可以由二极管固定，并且大大减少了泄漏。

公开(公告)号：US5381105A

公开(公告)日：1995-01-10

申请号：US017159

申请日：1993-02-12

申请人： John P. Phipps

发明人： John P. Phipps

IPC分类号： G01R31/28 ,  G01R31/3183 ,  G01R1/04

CPC分类号： G01R31/318371 ,  G01R31/2884

摘要： Testing of a semiconductor device (10, 30) is facilitated by forming the semiconductor device (10, 30) to have a first portion (17) that is electrically isolated from a second portion (19, 27). Testing is first performed on the first portion (17) of the semiconductor device (10, 30). After the testing is complete, the first portion (17) of the semiconductor device (10, 30) is electrically coupled to the second portion (19, 27) of the semiconductor device (10, 30) .

摘要翻译： 通过将半导体器件（10,30）形成为具有与第二部分（19,27）电隔离的第一部分（17），便于半导体器件（10,30）的测试。 首先在半导体器件（10,30）的第一部分（17）上进行测试。 在测试完成之后，半导体器件（10,30）的第一部分（17）电耦合到半导体器件（10,30）的第二部分（19,27）。

公开(公告)号：US5631187A

公开(公告)日：1997-05-20

申请号：US188975

申请日：1994-01-31

申请人： John P. Phipps ,  Stephen P. Robb ,  Judy L. Sutor ,  Lewis E. Terry

发明人： John P. Phipps ,  Stephen P. Robb ,  Judy L. Sutor ,  Lewis E. Terry

IPC分类号： H01L29/866 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78 ,  H01L29/861 ,  H03K17/08 ,  H03K17/16 ,  H01L21/70

CPC分类号： H01L29/7811 ,  H01L21/8221 ,  H01L27/0255 ,  H01L27/0688 ,  H01L29/7803 ,  H01L29/7808

摘要： A semiconductor device having an improved protection scheme and a temperature compensated sustaining voltage is provided by integrating a plurality of temperature compensated voltage reference diodes between the drain and the gate of the semiconductor device. The diodes protect the device by clamping the device's sustaining voltage to the total avalanche voltage of the diode. The device will dissipate any excessive energy in the conduction mode rather than in the more stressful avalanche mode. In addition, the plurality of diodes will provide for a temperature compensated sustaining voltage of the semiconductor device. The plurality of diodes are formed back-to-back in polysilicon. The positive temperature coefficient of the avalanching junction of each diode pair is compensated for by the negative temperature coefficient of the forward biased junction.

摘要翻译： 通过在半导体器件的漏极和栅极之间集成多个温度补偿电压参考二极管来提供具有改进的保护方案和温度补偿维持电压的半导体器件。 二极管通过将器件的维持电压钳位到二极管的总雪崩电压来保护器件。 该装置将在导通模式中消耗任何过多的能量，而不是在更紧张的雪崩模式下消耗。 此外，多个二极管将提供半导体器件的温度补偿维持电压。 在多晶硅中背对背地形成多个二极管。 每个二极管对的雪崩结的正温度系数由正向偏置结的负温度系数补偿。

公开(公告)号：US4419586A

公开(公告)日：1983-12-06

申请号：US296756

申请日：1981-08-27

申请人： John P. Phipps

发明人： John P. Phipps

IPC分类号： H01L31/12 ,  H01H35/00 ,  H03K17/687 ,  H03K17/78 ,  H03K17/785 ,  G02B27/00

CPC分类号： H03K17/6877 ,  H03K17/785

摘要： An improved solid state relay and regulator having reduced turn-off time, analog or digital input, and analog or digital output, is obtained by using a depletion JFET as a variable resistance discharge path for a gate of a power MOSFET switching device wherein the gate is charged by a first set of photovoltaic cells optically coupled to but electrically isolated from an LED input. A second set of photovoltaic cells responsive to the same or a separate LED input hold the JFET in an Off state while the MOSFET gate is energized. Variable output and AND logic are obtained.

摘要翻译： 通过使用耗尽JFET作为用于功率MOSFET开关器件的栅极的可变电阻放电路径来获得具有减少的截止时间，模拟或数字输入以及模拟或数字输出的改进的固态继电器和调节器，其中栅极 由第一组光电池充电，所述第一组光电池与LED输入端光耦合但电隔离。 响应于相同或单独的LED输入的第二组光伏电池在MOSFET栅极通电时将JFET保持在关闭状态。 获得可变输出和AND逻辑。

公开(公告)号：US5365099A

公开(公告)日：1994-11-15

申请号：US202856

申请日：1994-02-25

申请人： John P. Phipps ,  Stephen P. Robb ,  Judy L. Sutor ,  Lewis E. Terry

发明人： John P. Phipps ,  Stephen P. Robb ,  Judy L. Sutor ,  Lewis E. Terry

IPC分类号： H01L29/866 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78 ,  H01L29/861 ,  H03K17/08 ,  H03K17/16 ,  H01L29/10

CPC分类号： H01L29/7811 ,  H01L21/8221 ,  H01L27/0255 ,  H01L27/0688 ,  H01L29/7803 ,  H01L29/7808

摘要： A semiconductor device having an improved protection scheme and a temperature compensated sustaining voltage is provided by integrating a plurality of temperature compensated voltage reference diodes between the drain and the gate of the semiconductor device. The diodes protect the device by clamping the device's sustaining voltage to the total avalanche voltage of the diode. The device will dissipate any excessive energy in the conduction mode rather than in the more stressful avalanche mode. In addition, the plurality of diodes will provide for a temperature compensated sustaining voltage of the semiconductor device. The plurality of diodes are formed back-to-back in polysilicon. The positive temperature coefficient of the avalanching junction of each diode pair is compensated for by the negative temperature coefficient of the forward biased junction.

摘要翻译： 通过在半导体器件的漏极和栅极之间集成多个温度补偿电压参考二极管来提供具有改进的保护方案和温度补偿维持电压的半导体器件。 二极管通过将器件的维持电压钳位到二极管的总雪崩电压来保护器件。 该装置将在导通模式中消耗任何过多的能量，而不是在更紧张的雪崩模式下消耗。 此外，多个二极管将提供半导体器件的温度补偿维持电压。 在多晶硅中背对背地形成多个二极管。 每个二极管对的雪崩结的正温度系数由正向偏置结的负温度系数补偿。

公开(公告)号：US5115369A

公开(公告)日：1992-05-19

申请号：US637719

申请日：1991-01-07

申请人： Stephen P. Robb ,  John P. Phipps ,  Michael D. Gadberry

发明人： Stephen P. Robb ,  John P. Phipps ,  Michael D. Gadberry

IPC分类号： H01L27/02

CPC分类号： H01L27/0251

摘要： A power transistor having a control electrode which is coupled to a polysilicon JFET transistor is provided. In particular, a power MOSFET device having a polysilicon gate is formed and a JFET transistor is formed in the same polysilicon layer which forms the gate of the power MOSFET. A drain of the JFET forms an input terminal for the power MOSFET and a source of the JFET is coupled to the gate of the power MOSFET. A gate of the JFET is coupled to a gate-drain diode clamp so that when the gate-drain diode clamp is activated a portion of the current which is used to turn on the power MOSFET is channeled to the gate of the JFET and increases the drain-to-source series resistance of the JFET. The resistance of the JFET is low during normal operation and increases only when the gate-drain clamp is activated thus provides a high resistance during avalanche stress protection and a low resistance during normal operation.

摘要翻译： 提供了具有耦合到多晶硅JFET晶体管的控制电极的功率晶体管。 特别地，形成具有多晶硅栅极的功率MOSFET器件，并且在形成功率MOSFET的栅极的同一多晶硅层中形成JFET晶体管。 JFET的漏极形成用于功率MOSFET的输入端子，并且JFET的源极耦合到功率MOSFET的栅极。 JFET的栅极耦合到栅极 - 漏极二极管钳位，使得当栅极 - 漏极二极管钳位被激活时，用于接通功率MOSFET的电流的一部分被引导到JFET的栅极，并且增加 漏极到源极串联电阻的JFET。 在正常工作期间，JFET的电阻很低，只有当栅极 - 漏极钳位被激活时才增加，因此在雪崩应力保护期间提供高电阻，并在正常工作期间提供低电阻。

公开(公告)号：US5005061A

公开(公告)日：1991-04-02

申请号：US474889

申请日：1990-02-05

申请人： Stephen P. Robb ,  John P. Phipps ,  Michael D. Gadberry

发明人： Stephen P. Robb ,  John P. Phipps ,  Michael D. Gadberry

IPC分类号： H01L27/02

CPC分类号： H01L27/0251

摘要： A power transistor having a control electrode which is coupled to a polysilicon JFET transistor is provided. In particular, a power MOSFET device having a polysilicon gate is formed and a JFET transistor is formed in the same polysilicon layer which forms the gate of the power MOSFET. A drain of the JFET forms an input terminal for the power MOSFET and a source of the JFET is coupled to the gate of the power MOSFET. A gate of the JFET is copupled to a gate-drain diode clamp so that when the gate-drain diode clamp is activated a portion of the current which is used to turn on the power MOSFET is channeled to the gate of the JFET and increases the drain-to-source series resistance of the JFET. The resistance of the JFET is low during normal operation and increases only when the gate-drain clamp is activated thus provides a high resistance during avalanche stress protection and a low resistance during normal operation.

摘要翻译： 提供了具有耦合到多晶硅JFET晶体管的控制电极的功率晶体管。 特别地，形成具有多晶硅栅极的功率MOSFET器件，并且在形成功率MOSFET的栅极的同一多晶硅层中形成JFET晶体管。 JFET的漏极形成用于功率MOSFET的输入端子，并且JFET的源极耦合到功率MOSFET的栅极。 JFET的栅极被耦合到栅 - 漏二极管钳位，使得当栅极 - 漏极二极管钳位被激活时，用于接通功率MOSFET的电流的一部分被引导到JFET的栅极，并且增加 漏极到源极串联电阻的JFET。 在正常工作期间，JFET的电阻很低，只有当栅极 - 漏极钳位被激活时才增加，因此在雪崩应力保护期间提供高电阻，并在正常工作期间提供低电阻。