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    Field programmable logic device with dynamic interconnections to a dynamic logic core
    31.
    发明授权
    Field programmable logic device with dynamic interconnections to a dynamic logic core 失效
    具有与动态逻辑核心的动态互连的现场可编程逻辑器件

    公开(公告)号：US5596743A

    公开(公告)日：1997-01-21

    申请号：US369291

    申请日：1995-01-06

    申请人： Narasimha B. Bhat ,  Kamal Chaudhary

    发明人： Narasimha B. Bhat ,  Kamal Chaudhary

    IPC分类号： H03K19/173 ,  H03K19/177 ,  G06F19/00

    CPC分类号： H03K19/17728 ,  H03K19/17704

    摘要： The architecture, operation and design of a novel Field Programmable Logic Device is described. The device implements a circuit by using a dynamic logic core that executes staged logic corresponding to the logic levels of the implemented circuit. Logic inputs to the dynamic logic core are obtained from a dynamic interconnection array. Appropriate logic inputs for a given logic level are dynamically selected and routed by the dynamic interconnection array. When necessary, the dynamic interconnection array buffers signals which are required at subsequent logic levels. The dynamic interconnection array selects logic inputs for a given logic level from circuit input signals, buffered signals and dynamic logic core output signals.

    摘要翻译： 描述了一种新颖的现场可编程逻辑器件的架构，操作和设计。 该装置通过使用一个动态逻辑核实现一个电路，该逻辑核执行与被实现的电路的逻辑电平对应的分级逻辑。 从动态互连阵列获得动态逻辑核心的逻辑输入。 给定逻辑电平的适当逻辑输入由动态互连阵列动态选择和路由。 必要时，动态互连阵列缓冲后续逻辑电平所需的信号。 动态互连阵列从电路输入信号，缓冲信号和动态逻辑核心输出信号中选择给定逻辑电平的逻辑输入。

    Fanout-optimization during physical synthesis for placed circuit designs
    35.
    发明授权
    Fanout-optimization during physical synthesis for placed circuit designs 有权
    用于放置电路设计的物理合成期间的扇出优化

    公开(公告)号：US07853914B1

    公开(公告)日：2010-12-14

    申请号：US11827531

    申请日：2007-07-12

    申请人： Sankaranarayanan Srinivasan ,  Kamal Chaudhary ,  Amit Singh ,  Benoit Payette

    发明人： Sankaranarayanan Srinivasan ,  Kamal Chaudhary ,  Amit Singh ,  Benoit Payette

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： A method of implementing a circuit design for a target device can include assigning load pins of a high fanout signal of a placed circuit design into a plurality of windows according to a location of each load pin on the target device. A source of the high fanout signal can be replicated, wherein each window is associated with a source of the high fanout signal. For each source of the high fanout signal, the source can be connected to load pins of the window associated with the source and the source can be placed within the window associated with the source. The placed circuit design can be output.

    摘要翻译： 实现目标设备的电路设计的方法可以包括根据目标设备上的每个负载引脚的位置将放置的电路设计的高扇出信号的负载引脚分配到多个窗口中。 可以复制高扇出信号的源，其中每个窗口与高扇出信号的源相关联。 对于高扇出信号的每个源，源可以连接到与源相关联的窗口的负载引脚，并且源可以被放置在与源相关联的窗口内。 可以输出放置的电路设计。

    Programmable circuit optionally configurable as a lookup table or a wide multiplexer
    36.
    发明授权
    Programmable circuit optionally configurable as a lookup table or a wide multiplexer 有权
    可编程电路可选地配置为查找表或宽多路复用器

    公开(公告)号：US07075333B1

    公开(公告)日：2006-07-11

    申请号：US10925259

    申请日：2004-08-24

    申请人： Kamal Chaudhary ,  Philip D. Costello ,  Venu M. Kondapalli

    发明人： Kamal Chaudhary ,  Philip D. Costello ,  Venu M. Kondapalli

    IPC分类号： H03K19/173 ,  H03K19/177 ,  H01L25/00 ,  G06F7/38

    CPC分类号： H03K19/1737 ,  H03K19/17728

    摘要： Circuits that can be optionally programmed to function as lookup tables (LUTs) or wide multiplexers, and integrated circuits including these programmable circuits. A function select multiplexer is included between each memory cell and the corresponding data input terminal of a first multiplexer. Each function select multiplexer has a first data input terminal coupled to the corresponding memory cell, a second data input terminal coupled to an external input terminal, and a select terminal controlled by a value stored in a function select memory cell. When a first value is stored in the function select memory cell, the programmable circuit functions in the same fashion as a known LUT. When a second value is stored in the function select memory cell, the programmable circuit functions as a wide multiplexer, with the data input values being provided by the external input terminals.

    摘要翻译： 可选地编程为用作查找表（LUT）或多路复用器的电路，以及包括这些可编程电路的集成电路。 每个存储单元和第一多路复用器的对应的数据输入端之间包括功能选择多路复用器。 每个功能选择多路复用器具有耦合到对应的存储器单元的第一数据输入端子，耦合到外部输入端子的第二数据输入端子和由存储在功能选择存储器单元中的值控制的选择端子。 当第一值存储在功能选择存储单元中时，可编程电路以与已知LUT相同的方式起作用。 当第二个值存储在功能选择存储单元中时，可编程电路用作宽多路复用器，数据输入值由外部输入端提供。

    Relocation of components for post-placement optimization
    37.
    发明授权
    Relocation of components for post-placement optimization 有权
    迁移后的优化组件

    公开(公告)号：US07072815B1

    公开(公告)日：2006-07-04

    申请号：US10213775

    申请日：2002-08-06

    申请人： Kamal Chaudhary ,  Krishnan Anandh ,  Sudip K. Nag ,  Guenter Stenz

    发明人： Kamal Chaudhary ,  Krishnan Anandh ,  Sudip K. Nag ,  Guenter Stenz

    IPC分类号： G06F9/455

    CPC分类号： G06F17/5072

    摘要： Method and apparatus for post-placement optimization of resources for connections is described. To optimize resource placement, search windows are generated responsive to driver and load components, as well as to a connection between the driver and load components. Adding in a straight-line path search window may be used as an alternative where a bypassed resource is to be relocated. Using connection-based optimization in combination with driver- and resource-based optimization results in improved optimization with negligible impact on runtime.

    摘要翻译： 描述了用于连接资源的放置后优化的方法和装置。 为了优化资源放置，响应于驱动程序和加载组件以及驱动程序和加载组件之间的连接生成搜索窗口。 可以使用在直线路径搜索窗口中添加旁路资源被重新定位的替代方案。 使用基于连接的优化与基于驱动程序和资源的优化结合可以改善优化，对运行时的影响可以忽略不计。

    Pin reordering during placement of circuit designs
    38.
    发明授权
    Pin reordering during placement of circuit designs 有权
    电路设计放置期间引脚重新排序

    公开(公告)号：US07058915B1

    公开(公告)日：2006-06-06

    申请号：US10676445

    申请日：2003-09-30

    申请人： Amit Singh ,  Kamal Chaudhary

    发明人： Amit Singh ,  Kamal Chaudhary

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054 ,  G06F17/5072

    摘要： A method (400) of placing a circuit design can include the steps of identifying topological levels of a circuit design representation (415) and determining an arrival time for each input signal to a look up table within a circuit design representation (420). The propagation delay associated with each pin of the look up table can be identified (420) such that the input signals of the look up table can be ordered according to the arrival times of each input signal and the propagation delay of each pin of the look up table (435). The method can continue processing each look up table of an identified topological level (440) as well as each topological level of the circuit design representation (455).

    摘要翻译： 放置电路设计的方法（400）可以包括以下步骤：确定电路设计表示的拓扑水平（415）并且确定每个输入信号到电路设计表示（420）内的查找表的到达时间。 可以识别与查找表的每个引脚相关联的传播延迟（420），使得可以根据每个输入信号的到达时间和查看表的每个引脚的传播延迟来排序查找表的输入信号 （435）。 该方法可以继续处理所识别的拓扑级别（440）的每个查找表以及电路设计表示的每个拓扑级别（455）。

    Method and apparatus for automatic timing-driven implementation of a circuit design
    39.
    发明授权
    Method and apparatus for automatic timing-driven implementation of a circuit design 有权
    自动定时驱动实现电路设计的方法和装置

    公开(公告)号：US06484298B1

    公开(公告)日：2002-11-19

    申请号：US09574641

    申请日：2000-05-18

    申请人： Sudip K. Nag ,  Kamal Chaudhary ,  Jason H. Anderson ,  Madabhushi V. R. Chari ,  Sandor S. Kalman

    发明人： Sudip K. Nag ,  Kamal Chaudhary ,  Jason H. Anderson ,  Madabhushi V. R. Chari ,  Sandor S. Kalman

    IPC分类号： G06F1750

    CPC分类号： G06F17/5072 ,  G06F17/5077

    摘要： A method and apparatus for automatic, timing-driven implementation of a circuit design. In one embodiment, the different phases of implementing a circuit design are iteratively performed using timing constraints that are automatically and dynamically generated in each iteration. The process aids in identifying and achieving a maximum performance level of the implemented design. In another embodiment, selected numbers of critical connections are used to dynamically vary the timing constraint. In general, a number of connections is automatically selected from the circuit design and used to derive a new timing constraint to be applied in the next iteration. Slack values associated with paths in the design are also used in deriving the new timing constraint.

    摘要翻译： 一种用于电路设计的自动定时驱动实现的方法和装置。 在一个实施例中，使用在每次迭代中自动和动态生成的时序约束来迭代地执行实现电路设计的不同阶段。 该过程有助于确定并实现实施设计的最高性能水平。 在另一个实施例中，使用所选数量的关键连接来动态地改变时序约束。 通常，从电路设计中自动选择多个连接，并用于导出将在下一次迭代中应用的新的时序约束。 与设计中的路径相关联的松弛值也用于推导新的时序约束。