公开(公告)号：US20230086775A1

公开(公告)日：2023-03-23

申请号：US18072813

申请日：2022-12-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra MODY ,  Shashank DABRAL ,  Rajasekhar ALLU ,  Niraj NANDAN

IPC: H04N9/04 ,  G06T1/20 ,  H04N9/67

Abstract: An image signal processor includes a first matrix processing circuit, a post processing circuit, a second matrix processing circuit, and a split visual and analytics circuit. The first matrix processing circuit is configured to receive a plurality of component images generated based on an image captured by an image sensor and generate a plurality of first matrix outputs based on the plurality of component images. The post processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a first luminance component of the image and a chrominance component of the image. The second matrix processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a second luminance component of the image and a saturation component of the image. The split visual and analytics circuit is configured to generate visual and analytic data of the image.

公开(公告)号：US20220030202A1

公开(公告)日：2022-01-27

申请号：US17497560

申请日：2021-10-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra MODY ,  Shashank DABRAL ,  Rajasekhar ALLU ,  Niraj NANDAN

IPC: H04N9/04 ,  G06T1/20 ,  H04N9/67

Abstract: An image signal processor includes a first matrix processing circuit, a post processing circuit, a second matrix processing circuit, and a split visual and analytics circuit. The first matrix processing circuit is configured to receive a plurality of component images generated based on an image captured by an image sensor and generate a plurality of first matrix outputs based on the plurality of component images. The post processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a first luminance component of the image and a chrominance component of the image. The second matrix processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a second luminance component of the image and a saturation component of the image. The split visual and analytics circuit is configured to generate visual and analytic data of the image.

公开(公告)号：US20210326174A1

公开(公告)日：2021-10-21

申请号：US17138649

申请日：2020-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Niraj NANDAN ,  Mihir MODY

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/38 ,  G06F9/30

Abstract: A device includes a hardware data processing node configured to execute a respective task, and a hardware thread scheduler including a hardware task scheduler. The hardware task scheduler is coupled to the hardware data processing node and has a producer socket, a consumer socket, and a spare socket. The spare socket is configured to provide data control signals also provided by a first socket of the producer and consumer sockets responsive to a memory-mapped register being a first value. The spare socket is configured to provide data control signals also provided by a second socket of the producer and consumer sockets responsive to the memory-mapped register being a second value.

公开(公告)号：US20210209719A1

公开(公告)日：2021-07-08

申请号：US16847864

申请日：2020-04-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra MODY ,  Niraj NANDAN ,  Rajat SAGAR ,  Shashank DABRAL ,  Anthony LELL ,  Brijesh JADAV

IPC: G06T1/20 ,  G06T5/40 ,  G06T5/00 ,  G06T1/60

Abstract: A reconfigurable image processing pipeline includes an image signal processor (ISP), a control processor, and a local memory. ISP processes raw pixel data for a frame based on an image processing parameter and provides lines of processed pixel data to control processor via a first interface. For each region of interest (ROI) in the frame, ISP generates auto-exposure and auto-white balance (2A) statistics based on the lines for the ROI and writes them to the local memory via a second interface. Control processor reads 2A statistics from the local memory, determines the image processing parameter based on them, and provides the image processing parameter to ISP. ISP also generates an integer N bin histogram for control processor, which sums a portion of the N total bins and compares the summed bin count to a lighting transition threshold. The image processing parameter is further based on the comparison.

公开(公告)号：US20210027422A1

公开(公告)日：2021-01-28

申请号：US16911579

申请日：2020-06-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shashank DABRAL ,  Mihir Narendra MODY ,  Denis BEAUDOIN ,  Niraj NANDAN ,  Gang HUA

IPC: G06T3/40 ,  H04N9/04 ,  G06T5/00

Abstract: A method of de-mosaicing pixel data from an image processor includes generating a pixel block that includes a plurality of image pixels. The method also includes determining a first image gradient between a first set of pixels of the pixel block and a second image gradient between a second set of pixels of the pixel block. The method also includes determining a first adaptive threshold value based on intensity of a third set of pixels of the pixel block. The pixels of the third set of pixels are adjacent to one another. The method also includes filtering the pixel block in a vertical, horizontal, or neutral direction based on the first and second image gradients and the first adaptive threshold value utilizing a plurality of FIR filters to generate a plurality of component images.