公开(公告)号：US20200210351A1

公开(公告)日：2020-07-02

申请号：US16234508

申请日：2018-12-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir MODY ,  Niraj NANDAN ,  Hetul SANGHVI ,  Brian CHAE ,  Rajasekhar Reddy ALLU ,  Jason A.T. JONES ,  Anthony LELL ,  Anish REGHUNATH

IPC: G06F13/16 ,  G06F13/28 ,  H04N5/765 ,  G06T1/20

Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.

公开(公告)号：US20210209719A1

公开(公告)日：2021-07-08

申请号：US16847864

申请日：2020-04-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra MODY ,  Niraj NANDAN ,  Rajat SAGAR ,  Shashank DABRAL ,  Anthony LELL ,  Brijesh JADAV

IPC: G06T1/20 ,  G06T5/40 ,  G06T5/00 ,  G06T1/60

Abstract: A reconfigurable image processing pipeline includes an image signal processor (ISP), a control processor, and a local memory. ISP processes raw pixel data for a frame based on an image processing parameter and provides lines of processed pixel data to control processor via a first interface. For each region of interest (ROI) in the frame, ISP generates auto-exposure and auto-white balance (2A) statistics based on the lines for the ROI and writes them to the local memory via a second interface. Control processor reads 2A statistics from the local memory, determines the image processing parameter based on them, and provides the image processing parameter to ISP. ISP also generates an integer N bin histogram for control processor, which sums a portion of the N total bins and compares the summed bin count to a lighting transition threshold. The image processing parameter is further based on the comparison.

公开(公告)号：US20220114120A1

公开(公告)日：2022-04-14

申请号：US17558252

申请日：2021-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir MODY ,  Niraj NANDAN ,  Hetul SANGHVI ,  Brian CHAE ,  Rajasekhar Reddy ALLU ,  Jason A.T. JONES ,  Anthony LELL ,  Anish REGHUNATH

IPC: G06F13/16 ,  G06T1/20 ,  H04N5/765 ,  G06F13/28

Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.

公开(公告)号：US20210208657A1

公开(公告)日：2021-07-08

申请号：US17139249

申请日：2020-12-31

Applicant: Texas Instruments Incorporated

Inventor： Jose Luis FLORES ,  Gary Augustine COOPER ,  Amritpal Singh MUNDRA ,  Anthony LELL ,  Jason Lynn PECK

IPC: G06F1/3203 ,  G06F11/36

Abstract: An integrated circuit includes: a debugger; and an interface coupled to the debugger. The interface has: arbitration logic coupled to the debugger; a power processor coupled to the arbitration logic; and a power management network coupled to the power processor. The integrated circuit also includes subsystems coupled to the interface. The debugger is configured to perform debugging operations of the subsystems via the interface.

公开(公告)号：US20240077925A1

公开(公告)日：2024-03-07

申请号：US18505037

申请日：2023-11-08

Applicant: Texas Instruments Incorporated

Inventor： Jose Luis FLORES ,  Gary Augustine COOPER ,  Amritpal Singh MUNDRA ,  Anthony LELL ,  Jason Lynn PECK

IPC: G06F1/3203 ,  G06F11/36

CPC classification number: G06F1/3203 ,  G06F11/3656

Abstract: Circuits, systems and methods are provided. A circuit includes a subsystem, an interface, and a debugger. The interface includes power processing and management (PPM) circuitry coupled to the subsystem, and arbitration logic coupled to the PPM circuitry. In operation, the debugger issues a debug request to the arbitration logic to perform a debug operation on the subsystem, and, in response to the debug request, the arbitration logic provides an interrupt associated with the subsystem to the PPM circuitry. The PPM circuitry, in response to the interrupt and a determination that the subsystem is OFF, powers on the subsystem and provides a notification to the arbitration logic indicating that the subsystem is ON. The PPM circuitry also receives a notification from the arbitration logic that the debug operation related to the debug request is complete, and powers off the subsystem in response to that notification.

公开(公告)号：US20200379928A1

公开(公告)日：2020-12-03

申请号：US16995364

申请日：2020-08-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir MODY ,  Niraj NANDAN ,  Hetul SANGHVI ,  Brian CHAE ,  Rajasekhar Reddy ALLU ,  Jason A.T. JONES ,  Anthony LELL ,  Anish REGHUNATH

IPC: G06F13/16 ,  H04N5/765 ,  G06T1/20 ,  G06F13/28

Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.