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公开(公告)号：US20170161873A1
公开(公告)日：2017-06-08
申请号：US15349609
申请日：2016-11-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shashank DABRAL , Mihir Narendra MODY , Denis BEAUDOIN , Niraj NANDAN , Gang HUA
CPC classification number: G06T3/4015 , G06T3/403 , G06T2207/20012 , H04N9/045 , H04N2209/046
Abstract: A method of de-mosaicing pixel data from an image processor includes generating a pixel block that includes a plurality of image pixels. The method also includes determining a first image gradient between a first set of pixels of the pixel block and a second image gradient between a second set of pixels of the pixel block. The method also includes determining a first adaptive threshold value based on intensity of a third set of pixels of the pixel block. The pixels of the third set of pixels are adjacent to one another. The method also includes filtering the pixel block in a vertical, horizontal, or neutral direction based on the first and second image gradients and the first adaptive threshold value utilizing a plurality of FIR filters to generate a plurality of component images.
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公开(公告)号：US20210027422A1
公开(公告)日：2021-01-28
申请号：US16911579
申请日：2020-06-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shashank DABRAL , Mihir Narendra MODY , Denis BEAUDOIN , Niraj NANDAN , Gang HUA
Abstract: A method of de-mosaicing pixel data from an image processor includes generating a pixel block that includes a plurality of image pixels. The method also includes determining a first image gradient between a first set of pixels of the pixel block and a second image gradient between a second set of pixels of the pixel block. The method also includes determining a first adaptive threshold value based on intensity of a third set of pixels of the pixel block. The pixels of the third set of pixels are adjacent to one another. The method also includes filtering the pixel block in a vertical, horizontal, or neutral direction based on the first and second image gradients and the first adaptive threshold value utilizing a plurality of FIR filters to generate a plurality of component images.
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Patent Agency Ranking
3.发明申请公开(公告)号：US20200059311A1
公开(公告)日：2020-02-20
申请号：US16552353
申请日：2019-08-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Chunhua HU , Venkateswar Reddy KOWKUTLA , Eric HANSEN , Denis BEAUDOIN , Thomas Anton LEYRER
IPC: H04J3/06
Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.
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4.发明申请公开(公告)号：US20250030494A1
公开(公告)日：2025-01-23
申请号：US18909428
申请日：2024-10-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Chunhua HU , Venkateswar Reddy KOWKUTLA , Eric HANSEN , Denis BEAUDOIN , Thomas Anton LEYRER
Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.
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公开(公告)号：US20220408064A1
公开(公告)日：2022-12-22
申请号：US17895191
申请日：2022-08-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shashank DABRAL , Mihir Narendra MODY , Denis BEAUDOIN , Niraj NANDAN , Gang HUA
Abstract: A method of de-mosaicing pixel data from an image processor includes generating a pixel block that includes a plurality of image pixels. The method also includes determining a first image gradient between a first set of pixels of the pixel block and a second image gradient between a second set of pixels of the pixel block. The method also includes determining a first adaptive threshold value based on intensity of a third set of pixels of the pixel block. The pixels of the third set of pixels are adjacent to one another. The method also includes filtering the pixel block in a vertical, horizontal, or neutral direction based on the first and second image gradients and the first adaptive threshold value utilizing a plurality of FIR filters to generate a plurality of component images.
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6.发明申请公开(公告)号：US20220368444A1
公开(公告)日：2022-11-17
申请号：US17876662
申请日：2022-07-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Chunhua HU , Venkateswar Reddy KOWKUTLA , Eric HANSEN , Denis BEAUDOIN , Thomas Anton LEYRER
IPC: H04J3/06
Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.
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7.发明申请公开(公告)号：US20180227067A1
公开(公告)日：2018-08-09
申请号：US15891227
申请日：2018-02-07
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Chunhua HU , Venkateswar Reddy KOWKUTLA , Eric HANSEN , Denis BEAUDOIN , Thomas Anton LEYRER
IPC: H04J3/06
CPC classification number: H04J3/0658 , H04J3/0641 , H04J3/0667 , H04J3/0676 , H04J3/0679 , H04J3/0688 , H04J3/0691 , H04L7/0083
Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.
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