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公开(公告)号：US20200210351A1
公开(公告)日：2020-07-02
申请号：US16234508
申请日：2018-12-27
发明人： Mihir MODY , Niraj NANDAN , Hetul SANGHVI , Brian CHAE , Rajasekhar Reddy ALLU , Jason A.T. JONES , Anthony LELL , Anish REGHUNATH
摘要： A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.
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公开(公告)号：US20210209390A1
公开(公告)日：2021-07-08
申请号：US16745589
申请日：2020-01-17
摘要： An image data frame is received from an external source. An error concealment operation is performed on the received image data frame in response to determining that a first frame size of the received image data frame is erroneous. The first frame size of the image data frame is determined to be erroneous based on at least one frame synchronization signal associated with the image data frame. An image processing operation is performed on the received image data frame on which the error concealment operation has been performed, thereby enabling an image processing module to perform the image processing operation without entering into a deadlock state and thereby prevent a host processor from having to execute hardware resets of deadlocked modules.
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公开(公告)号：US20220114120A1
公开(公告)日：2022-04-14
申请号：US17558252
申请日：2021-12-21
发明人： Mihir MODY , Niraj NANDAN , Hetul SANGHVI , Brian CHAE , Rajasekhar Reddy ALLU , Jason A.T. JONES , Anthony LELL , Anish REGHUNATH
摘要： A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.
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公开(公告)号：US20200379928A1
公开(公告)日：2020-12-03
申请号：US16995364
申请日：2020-08-17
发明人： Mihir MODY , Niraj NANDAN , Hetul SANGHVI , Brian CHAE , Rajasekhar Reddy ALLU , Jason A.T. JONES , Anthony LELL , Anish REGHUNATH
摘要： A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.
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5.发明公开公开(公告)号：US20240005449A1
公开(公告)日：2024-01-04
申请号：US18467940
申请日：2023-09-15
CPC分类号： G06T3/4023 , G06V10/32 , G06V10/96 , G06V10/993 , H04N1/00021 , H04N1/00034 , H04N1/00005 , H04N1/00082 , G06T2207/10016
摘要： An image data frame is received from an external source. An error concealment operation is performed on the received image data frame in response to determining that a first frame size of the received image data frame is erroneous. The first frame size of the image data frame is determined to be erroneous based on at least one frame synchronization signal associated with the image data frame. An image processing operation is performed on the received image data frame on which the error concealment operation has been performed, thereby enabling an image processing module to perform the image processing operation without entering into a deadlock state and thereby prevent a host processor from having to execute hardware resets of deadlocked modules.
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公开(公告)号：US20220012312A1
公开(公告)日：2022-01-13
申请号：US17487517
申请日：2021-09-28
摘要： In some examples, a system includes storage storing a machine learning model, wherein the machine learning model comprises a plurality of layers comprising multiple weights. The system also includes a processing unit coupled to the storage and operable to group the weights in each layer into a plurality of partitions; determine a number of least significant bits to be used for watermarking in each of the plurality of partitions; insert one or more watermark bits into the determined least significant bits for each of the plurality of partitions; and scramble one or more of the weight bits to produce watermarked and scrambled weights. The system also includes an output device to provide the watermarked and scrambled weights to another device.
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公开(公告)号：US20210326174A1
公开(公告)日：2021-10-21
申请号：US17138649
申请日：2020-12-30
发明人： Niraj NANDAN , Mihir MODY
摘要： A device includes a hardware data processing node configured to execute a respective task, and a hardware thread scheduler including a hardware task scheduler. The hardware task scheduler is coupled to the hardware data processing node and has a producer socket, a consumer socket, and a spare socket. The spare socket is configured to provide data control signals also provided by a first socket of the producer and consumer sockets responsive to a memory-mapped register being a first value. The spare socket is configured to provide data control signals also provided by a second socket of the producer and consumer sockets responsive to the memory-mapped register being a second value.
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公开(公告)号：US20190205508A1
公开(公告)日：2019-07-04
申请号：US16188560
申请日：2018-11-13
CPC分类号： G06F21/16 , G06N3/0472 , G06N20/00
摘要： In some examples, a system includes storage storing a machine learning model, wherein the machine learning model comprises a plurality of layers comprising multiple weights. The system also includes a processing unit coupled to the storage and operable to group the weights in each layer into a plurality of partitions; determine a number of least significant bits to be used for watermarking in each of the plurality of partitions; insert one or more watermark bits into the determined least significant bits for each of the plurality of partitions; and scramble one or more of the weight bits to produce watermarked and scrambled weights. The system also includes an output device to provide the watermarked and scrambled weights to another device.
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