公开(公告)号：US20200013634A1

公开(公告)日：2020-01-09

申请号：US16027558

申请日：2018-07-05

Applicant: Texas Instruments Incorporated

Inventor： Sadia Naseem ,  Vikas Gupta

IPC: H01L21/48 ,  H01L23/495

Abstract: The disclosed principles provide for implementing low-cost and fast metallic printing processes into the QFN and other no-leads package assembly flow to selectively print solderable material in areas that would otherwise be susceptible to corrosion and thus pose reliability risks. The problem of copper corrosion and poor BLR performance in no-leads packages because of remaining exposed copper areas after package singulation is solved by employing selective metallic printing processes in the assembly flow to coat all risk-prone areas with solder material. For example, for no-leads packages that are formed using printed leadframes, solder can be deposited through inkjet, screen, stencil, or photonic printing into the grooves which are formed after passivating the packages at the strip level. The singulating occurs through the grooves having solder printed therein, and results in wettable upper and sidewall surfaces of the outer ends of the leadframe for each package.

公开(公告)号：US10475729B2

公开(公告)日：2019-11-12

申请号：US16252412

申请日：2019-01-18

Applicant: Texas Instruments Incorporated

Inventor： Vikas Gupta ,  Daniel Yong Lin

IPC: H01L23/495 ,  H01L23/31

Abstract: A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.

公开(公告)号：US20190019776A1

公开(公告)日：2019-01-17

申请号：US15646976

申请日：2017-07-11

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer ,  Minhong Mi ,  Swaminathan Sankaran ,  Rajen M. Murugan ,  Vikas Gupta

IPC: H01L25/065 ,  H01L23/31 ,  H01L49/02 ,  H01L23/495 ,  H01L23/00

Abstract: Described examples include a packaged device including a first object and a second object spaced from each other by a gap, each object having a first surface and an opposite second surface, the first surfaces of the first object and the second object including first terminals. A structure includes at least two conductors embedded in a dielectric casing consolidating a configuration and organization of the at least two conductors, the at least two conductors having end portions un-embedded by the dielectric casing. An end portion of at least one of the at least two conductors is electrically connected to a first terminal of the first object, and an opposite end portion of the at least one of the at least two conductors is electrically connected to a respective first terminal of the second object, the at least two conductors electrically connecting the first object and the second object.

公开(公告)号：US20180190608A1

公开(公告)日：2018-07-05

申请号：US15840497

申请日：2017-12-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vikas Gupta ,  Daniel Yong Lin

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L24/16 ,  H01L21/4825 ,  H01L21/4828 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49503 ,  H01L23/49517 ,  H01L23/49531 ,  H01L23/49541 ,  H01L23/49582 ,  H01L23/49586 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/10175 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/16258 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A packaged semiconductor device includes a lead frame and a semiconductor device. A solder joint is coupled between the lead frame and a terminal on the semiconductor device. A reflow wall is on a portion of the lead frame and is in contact with the solder joint. A molding compound covers portions of the semiconductor device, the lead frame, the solder joint, and the reflow wall.

公开(公告)号：US11735806B2

公开(公告)日：2023-08-22

申请号：US16151441

申请日：2018-10-04

Applicant: Texas Instruments Incorporated

Inventor： Vikas Gupta ,  Meysam Moallem ,  Sadia Naseem

IPC: H01Q1/22 ,  H01Q1/50 ,  H01L23/66 ,  H01Q21/00 ,  H01L23/498 ,  H01Q1/52 ,  H01Q13/02 ,  H01Q1/32

CPC classification number: H01Q1/2283 ,  H01L23/49838 ,  H01L23/66 ,  H01Q1/3233 ,  H01Q1/50 ,  H01Q1/525 ,  H01Q13/02 ,  H01Q21/0006 ,  H01L2223/6627 ,  H01L2223/6677

Abstract: A high frequency wireless device includes a three-dimensional (3D) antenna structure mounted on a PCB including a first antenna connected to a first waveguide feed and second antenna connected to a second waveguide feed. A packaged device on the PCB has a top metal surface including a transmit (Tx) radiating structure under the second waveguide feed and a receive (Rx) radiating structure under the first waveguide feed, and an RF connection from the top metal surface to its bottom surface. An IC die is flipchip attached to the bottom surface including at least one Rx channel and at least one Tx channel connected by the RF connection to the Rx and Tx radiating structures. Protruding metal features are on the dielectric layer under the first and second waveguide feeds on ≥2 sides of the Tx and the Rx radiating structure to create a waveguiding wall structure for directing signals.

公开(公告)号：US11128023B2

公开(公告)日：2021-09-21

申请号：US16716642

申请日：2019-12-17

Applicant: Texas Instruments Incorporated

Inventor： Hassan Omar Ali ,  Juan Alejandro Herbsommer ,  Benjamin Stassen Cook ,  Vikas Gupta ,  Athena Lin ,  Swaminathan Sankaran

IPC: H01P3/16 ,  H01Q1/22 ,  H04B1/40 ,  H01P3/12

Abstract: A device includes a multilayer substrate having a first surface and a second surface opposite the first surface. An integrated circuit is mounted on the second surface of the multilayer substrate, the integrated circuit having transmission circuitry configured to process millimeter wave signals. A substrate waveguide having a substantially solid wall is formed within a portion of the multilayer substrate perpendicular to the first surface. The substrate waveguide has a first end with the wall having an edge exposed on the first surface of the multilayer substrate. A reflector is located in one of the layers of the substrate and is coupled to an edge of the wall on an opposite end of the substrate waveguide.

公开(公告)号：US20210166951A1

公开(公告)日：2021-06-03

申请号：US17172043

申请日：2021-02-09

Applicant: Texas Instruments Incorporated

Inventor： Sadia Naseem ,  Vikas Gupta

IPC: H01L21/48 ,  H01L23/495

Abstract: The disclosed principles provide for implementing low-cost and fast metallic printing processes into the QFN and other no-leads package assembly flow to selectively print solderable material in areas that would otherwise be susceptible to corrosion and thus pose reliability risks. The problem of copper corrosion and poor BLR performance in no-leads packages because of remaining exposed copper areas after package singulation is solved by employing selective metallic printing processes in the assembly flow to coat all risk-prone areas with solder material. For example, for no-leads packages that are formed using printed leadframes, solder can be deposited through inkjet, screen, stencil, or photonic printing into the grooves which are formed after passivating the packages at the strip level. The singulating occurs through the grooves having solder printed therein, and results in wettable upper and sidewall surfaces of the outer ends of the leadframe for each package.

公开(公告)号：US20180277461A1

公开(公告)日：2018-09-27

申请号：US15470486

申请日：2017-03-27

Applicant: Texas Instruments Incorporated

Inventor： Rongwei Zhang ,  Vikas Gupta

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

Abstract: Described examples include a device including a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of the surface area of the second surface. The adhesive layer includes first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous. The first polymeric compound has a first modulus and the second polymeric compound has a second modulus greater than the first modulus.