公开(公告)号：US20240071998A1

公开(公告)日：2024-02-29

申请号：US17893354

申请日：2022-08-23

申请人： Taiwan Semiconductor Manufacturing Company

发明人： Li-Hsien Huang ,  Hsueh-Lung Cheng ,  Yao-Chun Chuang ,  Yinlung Lu

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/10

CPC分类号： H01L25/0655 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/96 ,  H01L25/18 ,  H01L2224/05073 ,  H01L2224/05555 ,  H01L2224/05564 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/06134 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16258 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/95001 ,  H01L2224/96

摘要： A method of packaging a semiconductor includes: positioning first and second semiconductor dies by one another on a carrier substrate, wherein first and second zones zone are defined with respect to the first die and third and fourth zones are defined with respect to the second die; forming first vias in the first zone, the first vias having a first size; forming second vias in the second zone, the second vias having a second size different from the first; forming third vias in the third zone, the third vias having a third size; forming fourth vias in the fourth zone, the fourth vias having a fourth size different from the third; and electrically connecting the first and second dies with an interconnection die such that electrical signals are exchangeable therebetween.

公开(公告)号：US20190198375A1

公开(公告)日：2019-06-27

申请号：US16293168

申请日：2019-03-05

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Darrell D. TRUHITTE ,  James P. LETTERMAN, JR.

IPC分类号： H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC分类号： H01L21/6835 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/49537 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/11003 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11418 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/116 ,  H01L2224/119 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/1319 ,  H01L2224/16245 ,  H01L2224/16258 ,  H01L2224/27003 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/27418 ,  H01L2224/2746 ,  H01L2224/27462 ,  H01L2224/276 ,  H01L2224/279 ,  H01L2224/2908 ,  H01L2224/291 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/33181 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/4811 ,  H01L2224/48111 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/753 ,  H01L2224/75755 ,  H01L2224/75756 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81856 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83805 ,  H01L2224/83815 ,  H01L2224/83856 ,  H01L2224/85005 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/92147 ,  H01L2224/92227 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/27 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/207

摘要： Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.

公开(公告)号：US09892952B2

公开(公告)日：2018-02-13

申请号：US14341454

申请日：2014-07-25

申请人： Semiconductor Components Industries, LLC

发明人： Darrell Truhitte ,  James P. Letterman, Jr.

IPC分类号： H01L21/683 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/36 ,  H01L23/495

CPC分类号： H01L21/6835 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/49537 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/11003 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11418 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/116 ,  H01L2224/119 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/1319 ,  H01L2224/16245 ,  H01L2224/16258 ,  H01L2224/27003 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/27418 ,  H01L2224/2746 ,  H01L2224/27462 ,  H01L2224/276 ,  H01L2224/279 ,  H01L2224/2908 ,  H01L2224/291 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/33181 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/4811 ,  H01L2224/48111 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/753 ,  H01L2224/75755 ,  H01L2224/75756 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81856 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83805 ,  H01L2224/83815 ,  H01L2224/83856 ,  H01L2224/85005 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/92147 ,  H01L2224/92227 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/27 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/207

摘要： Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.

公开(公告)号：US09219025B1

公开(公告)日：2015-12-22

申请号：US14460463

申请日：2014-08-15

申请人： Infineon Technologies AG

发明人： Swee Kah Lee ,  Chee Hong Fang ,  Mei Chin Ng

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/29

CPC分类号： H01L23/49503 ,  H01L21/4828 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/565 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49541 ,  H01L23/49582 ,  H01L23/49861 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/16258 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/0133 ,  H01L2924/1711 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2224/81 ,  H01L2924/00014

摘要： A molded flip-chip semiconductor package includes a leadframe having opposing first and second main surfaces, a first metallization on the first main surface, a second metallization on the second main surface, recessed regions which extend from the second main surface toward the first main surface, and spaced apart leads chemically etched into the leadframe between gaps in the first metallization. The package further includes a semiconductor die having a plurality of pads facing and attached to the leads of the leadframe, a first molding compound that fills the recessed regions, and a second molding compound that encases the semiconductor die and fills the space between the leads such that the second molding compound abuts the first molding compound. A is the overall thickness of the leadframe, B is the spacing between adjacent ones of the leads, and B/A

摘要翻译： 模制倒装芯片半导体封装包括具有相对的第一和第二主表面的引线框架，第一主表面上的第一金属化，第二主表面上的第二金属化，从第二主表面朝向第一主表面延伸的凹陷区域 并且在第一金属化间隙中间隔开的引线被化学蚀刻到引线框架中。 该封装还包括半导体管芯，该半导体管芯具有面向并连接到引线框架的引线的多个焊盘，填充凹陷区域的第一模塑料和封装半导体管芯并填充引线之间的空间的第二模塑料， 第二模塑料邻接第一模塑料。 A是引线框架的总厚度，B是相邻引线之间的间距，B / A <1。

公开(公告)号：US09196533B2

公开(公告)日：2015-11-24

申请号：US13642229

申请日：2011-04-18

申请人： Naohide Takamoto ,  Goji Shiga

发明人： Naohide Takamoto ,  Goji Shiga

IPC分类号： H01L21/00 ,  H01L23/28 ,  H01L23/29 ,  H01L21/78 ,  H01L21/683 ,  C09J7/02 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L21/78 ,  C09J7/20 ,  C09J2203/326 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/293 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68377 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16258 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01L2924/351 ,  Y10T428/14 ,  H01L2924/01082 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/00

摘要： The present invention relates to a film for back surface of flip-chip semiconductor, which is to be formed on a back surface of a semiconductor element flip-chip connected onto an adherend, wherein an amount of shrinkage of the film for back surface of flip-chip semiconductor due to thermal curing is 2% by volume or more and not more than 30% by volume relative to a total volume of the film for back surface of flip-chip semiconductor before the thermal curing. According to the film for back surface of flip-chip semiconductor according to the present invention, since it is formed on the back surface of a semiconductor element having been flip-chip connected onto an adherend, it fulfills a function to protect the semiconductor element. In addition, in the film for back surface of flip-chip semiconductor according to the present invention, since an amount of shrinkage due to thermal curing is 2% by volume or more relative to a total volume of the film for back surface of flip-chip semiconductor before the thermal curing, a warp of a semiconductor element to be generated at the time of flip-chip connecting the semiconductor element onto an adherend can be effectively suppressed or prevented.

摘要翻译： 本发明涉及一种倒装芯片半导体背面用薄膜，其用于形成在与被粘物相连的半导体元件倒装芯片的背面上，其中，用于后翻表面的薄膜的收缩量 由于热固化，芯片半导体相对于热固化前的倒装芯片用半导体膜的总体积为2体积％以上且30体积％以下。 根据本发明的倒装芯片半导体的背面用薄膜，由于形成在倒装芯片连接在被粘物上的半导体元件的背面，所以具有保护半导体元件的功能。 另外，在本发明的倒装芯片半导体的背面用膜中，由于热固化时的收缩量相对于翻转半导体背面用膜的总体积为2体积％以上， 在热固化之前的芯片半导体，可以有效地抑制或防止将半导体元件倒装芯片连接到被粘物体时产生的半导体元件的翘曲。

公开(公告)号：US09165910B2

公开(公告)日：2015-10-20

申请号：US14564502

申请日：2014-12-09

申请人： Micron Technology, Inc.

发明人： Meow Koon Eng ,  Yong Poo Chia ,  Suan Jeung Boon

IPC分类号： H01L25/10 ,  H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L21/50 ,  H01L23/31

CPC分类号： H01L25/105 ,  H01L21/50 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49555 ,  H01L23/49811 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/17 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16258 ,  H01L2224/17106 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

摘要： Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing.

摘要翻译： 本文公开了微电子管芯封装，管芯封装的堆叠系统及其制造方法。 在一个实施例中，堆叠封装的系统包括具有底侧的第一裸片封装，第一电介质外壳和第一金属引线; 第二管芯封装，其具有附接到第一封装的底侧的顶侧，具有侧面的电介质外壳和与第一金属引线对准并朝向第一金属引线突出的第二金属引线，并且包括外表面和内表面区域， 一般面向外侧; 和金属焊接连接器将各个第一引线连接到单独的第二引线。 在另一个实施例中，各个第二引线具有“L”形状并且物理地接触相应的单个第一引线。 在另一个实施例中，各个第二引线具有“C”形并且包括向第二壳体的侧面突出的分层部分。

公开(公告)号：US20150289365A1

公开(公告)日：2015-10-08

申请号：US14247530

申请日：2014-04-08

申请人： Apple Inc.

发明人： Christopher V. Hunat ,  Annabelle Q. Yang

IPC分类号： H05K1/02 ,  H05K1/03 ,  H01L23/552 ,  H01L27/146 ,  H01L23/498

CPC分类号： H01L23/552 ,  H01L23/13 ,  H01L24/13 ,  H01L24/16 ,  H01L27/14618 ,  H01L27/14634 ,  H01L2224/131 ,  H01L2224/16258 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15156 ,  H01L2924/15157 ,  H01L2924/15159 ,  H01L2924/15162 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19105 ,  H05K1/0306 ,  H05K1/181 ,  H05K3/242 ,  H05K3/403 ,  H05K2201/0715 ,  H05K2201/09072 ,  H05K2201/09781 ,  H05K2201/10121 ,  H05K2201/2018 ,  H01L2924/014

摘要： A dielectric substrate may serve as a circuit carrier for integrated circuits and other electrical components. The dielectric substrate may be formed from a dielectric material such as a ceramic substrate material, a printed circuit board substrate material, or other substrate material. The dielectric substrate may have a rectangular outline with four peripheral edge surfaces. The dielectric material may contain multiple layers that are laminated together and may support metal traces forming contacts and other interconnects. Integrated circuits and other electrical components may be mounted to the contacts. The metal traces may include electroplating lines that extend inwardly. The dielectric material may have a rectangular ring shape with a central rectangular opening having inner edge surfaces. The electroplating lines may be exposed along the inner edge surfaces. The four peripheral edge surfaces may be provided with a conductive electromagnetic interference shielding layer.

摘要翻译： 电介质基板可以用作集成电路和其它电气部件的电路载体。 电介质基板可以由诸如陶瓷基板材料，印刷电路板基板材料或其它基板材料的介电材料形成。 电介质基板可以具有四个周边边缘表面的矩形轮廓。 电介质材料可以包含层叠在一起的多个层，并且可以支撑形成接触和其它互连的金属迹线。 集成电路和其他电气部件可以安装到触点。 金属迹线可以包括向内延伸的电镀线。 电介质材料可以具有矩形环形，具有具有内边缘表面的中心矩形开口。 电镀线可能沿着内边缘表面露出。 四个周边边缘表面可以设置有导电电磁干扰屏蔽层。

公开(公告)号：US20140015130A1

公开(公告)日：2014-01-16

申请号：US14029455

申请日：2013-09-17

申请人： Micron Technology, Inc.

发明人： Meow Koon Eng ,  Yong Poo Chia ,  Suan Jeung Boon

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L25/105 ,  H01L21/50 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49555 ,  H01L23/49811 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/17 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16258 ,  H01L2224/17106 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

摘要： Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing.

摘要翻译： 本文公开了微电子管芯封装，管芯封装的堆叠系统及其制造方法。 在一个实施例中，堆叠封装的系统包括具有底侧的第一裸片封装，第一电介质外壳和第一金属引线; 第二管芯封装，其具有附接到第一封装的底侧的顶侧，具有侧面的电介质外壳和与第一金属引线对准并朝向第一金属引线突出的第二金属引线，并且包括外表面和内表面区域， 一般面向外侧; 和金属焊接连接器将各个第一引线连接到单独的第二引线。 在另一个实施例中，各个第二引线具有“L”形状并且物理地接触相应的单个第一引线。 在另一个实施例中，各个第二引线具有“C”形并且包括向第二壳体的侧面突出的分层部分。

公开(公告)号：US08492907B2

公开(公告)日：2013-07-23

申请号：US13186000

申请日：2011-07-19

申请人： Naohide Takamoto ,  Goji Shiga ,  Fumiteru Asai

发明人： Naohide Takamoto ,  Goji Shiga ,  Fumiteru Asai

IPC分类号： H01L23/48 ,  H01L21/50 ,  B32B3/00

CPC分类号： H01L21/6835 ,  C09J163/00 ,  H01L21/561 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16258 ,  H01L2224/16268 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81002 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/831 ,  H01L2224/83862 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/15788 ,  Y10T428/24802 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2224/13099

摘要： The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, the film having a light transmittance at a wavelength of 532 nm or 1064 nm of 20% or less, and having a contrast between a marking part and a part other than the marking part after laser marking of 20% or more.

摘要翻译： 本发明涉及一种用于倒装芯片型半导体背表面的薄膜，该薄膜形成在连接到被粘物上的半导体元件倒装芯片的背面上，该膜具有波长为532nm或1064nm的透光率为20 ％以下，并且在激光标记20％以上之后，在标记部和标记部以外的部分之间具有对比度。

公开(公告)号：US20130065361A1

公开(公告)日：2013-03-14

申请号：US13232946

申请日：2011-09-14

申请人： Geng-Shin Shen

发明人： Geng-Shin Shen

IPC分类号： H01L21/78

CPC分类号： H01L24/81 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49861 ,  H01L24/13 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/10175 ,  H01L2224/1134 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/14151 ,  H01L2224/14155 ,  H01L2224/16245 ,  H01L2224/16257 ,  H01L2224/16258 ,  H01L2224/81193 ,  H01L2224/81856 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/05552

摘要： A method for manufacturing a semiconductor package structure is disclosed. In one embodiment, the method includes the steps of forming a plurality of conductive pastes on a matrix lead frame with a groove located within a predetermined distance from each conductive paste on the lead; partially curing the conductive pastes so that the conductive pastes are in a semi-cured state; preparing at least one chip with a plurality of bumps thereon; electrically connecting the chip and the lead by implanting the bumps into the semi-cured conductive pastes, wherein the groove on the lead of the matrix lead frame is configured to receive overflowed semi-cured conductive pastes; curing the semi-cured conductive pastes to completely secure the bumped chip; and forming an encapsulating material covering the lead frame and the chip. The method can also be applied in pre-molded lead frame package.

摘要翻译： 公开了半导体封装结构的制造方法。 在一个实施例中，该方法包括以下步骤：在矩阵引线框架上形成多个导电浆料，其中凹槽位于与引线上的每个导电浆料预定距离内; 部分固化导电浆料，使得导电浆料处于半固化状态; 制备其上具有多个凸块的至少一个芯片; 通过将凸块植入到半固化的导电浆料中来将芯片和引线电连接，其中，矩阵引线框架的引线上的槽被配置为接收溢出的半固化的导电浆料; 固化半固化导电浆料以完全固定凸起的芯片; 以及形成覆盖引线框和芯片的封装材料。 该方法也可应用于预成型引线框架封装中。