公开(公告)号：US20190035757A1

公开(公告)日：2019-01-31

申请号：US16022704

申请日：2018-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Chun-Hui Yu

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L25/065 ,  H01L23/538

Abstract: A semiconductor package has at least one die, a first redistribution layer and a second redistribution layer. The first redistribution layer includes a first dual damascene redistribution pattern having a first via portion and a first routing portion. The second redistribution layer is disposed on the first redistribution layer and over the first die and electrically connected with the first redistribution layer and the first die. The second redistribution layer includes a second dual damascene redistribution pattern having a second via portion and a second routing portion. A location of the second via portion is aligned with a location of first via portion.

公开(公告)号：US10177078B2

公开(公告)日：2019-01-08

申请号：US15372918

申请日：2016-12-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Chun-Hui Yu

IPC: H01L21/56 ,  H01L23/485 ,  H01L25/065 ,  H01L23/29 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L23/31

Abstract: Chip package structures and methods for forming the same are provided. The chip package structure includes a first protection layer and a first chip disposed over the first protection layer. The chip package structure further includes a first photosensitive layer surrounding the first chip and covering the first chip and a redistribution layer formed over the first photosensitive layer.

公开(公告)号：US10157864B1

公开(公告)日：2018-12-18

申请号：US15662279

申请日：2017-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Kuo-Chung Yee

IPC: H01L23/52 ,  H01L23/00 ,  H01L23/31

Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, and an RDL structure. The encapsulant is aside the die, and the RDL structure is electrically connected to the die. The RDL structure includes a first dielectric layer and a first RDL. The first dielectric layer is disposed on the encapsulant and the die. The first RDL is embedded in the first dielectric layer. The first RDL includes a seed layer and a conductive layer. The seed layer surrounds sidewalls of the conductive layer, and is disposed between the conductive layer and the first dielectric layer.

公开(公告)号：US20180012863A1

公开(公告)日：2018-01-11

申请号：US15202541

申请日：2016-07-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Kuo-Chung Yee

IPC: H01L25/065 ,  H01L21/3105 ,  H01L21/683 ,  H01L21/768 ,  H01L27/146 ,  H01L25/00 ,  G06K9/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56

CPC classification number: H01L25/0652 ,  G06K9/00006 ,  H01L21/31051 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3157 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L25/50 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687 ,  H01L2221/68331 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02333

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a first redistribution layer, a first die over the first redistribution layer, a molding compound encapsulating at least one second die and at least one third die disposed on the first redistribution layer, and at least one fourth die and conductive elements connected to the first redistribution layer. Through vias of the first die are electrically connected to through interlayer vias penetrating through the molding compound and are electrically connected to the first redistribution layer. The semiconductor package may further include a second redistribution layer disposed on the molding compound and between the first die, the second die and the third die.