公开(公告)号：US11183560B2

公开(公告)日：2021-11-23

申请号：US16681097

申请日：2019-11-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  I-Sheng Chen ,  Tzu-Chiang Chen ,  Shih-Syuan Huang ,  Hung-Li Chiang

IPC: H01L29/76 ,  H01L31/113 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L21/8234

Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure further includes a first source/drain structure formed adjacent to the first nanostructures and a second source/drain structure formed adjacent to the second nanostructures. The semiconductor structure further includes a first contact plug formed over the first source/drain structure and a second contact plug formed over the second source/drain structure. In addition, a bottom portion of the first contact plug is lower than a bottom portion of the first nanostructures, and a bottom portion of the second contact plug is higher than a top portion of the second nanostructures.

公开(公告)号：US11177387B2

公开(公告)日：2021-11-16

申请号：US16725572

申请日：2019-12-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng Chen ,  Chih Chieh Yeh ,  Cheng-Hsien Wu

IPC: H01L29/786 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/10 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/08

Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire extends into the source/drain region. The semiconductor wire in the source/drain regions is wrapped around by a second semiconductor material.

公开(公告)号：US11081592B2

公开(公告)日：2021-08-03

申请号：US16196329

申请日：2018-11-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng Chen ,  Szu-Wei Huang ,  Hung-Li Chiang ,  Cheng-Hsien Wu ,  Chih Chieh Yeh

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/775 ,  H01L29/04 ,  H01L21/8238 ,  H01L27/04

Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a core region, and one or more shell regions. The core region has an approximately square-shape cross section and a first shell of the one or more shells forms a first shell region of an approximately rhombus-shape cross section around the core region and is connected to an adjacent first shell region corresponding to a neighboring semiconductor wire.

公开(公告)号：US11056401B2

公开(公告)日：2021-07-06

申请号：US16700227

申请日：2019-12-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng Chen ,  Tzu-Chiang Chen ,  Cheng-Hsien Wu ,  Chih-Chieh Yeh ,  Chih-Sheng Chang

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02

Abstract: A semiconductor device includes a first source/drain feature adjoining first nanostructures, and a first multilayer work function structure surrounding the first nanostructures. The first multilayer work function structure includes a first middle dielectric layer around the first nanostructures and a first metal layer around and in contact with the first middle dielectric layer. The semiconductor device also includes a second source/drain feature adjoining second nanostructures, and a second multilayer work function structure surrounding the second nanostructures. The second multilayer work function structure includes a second middle dielectric layer around the second nanostructures and a second metal layer around and in contact with the second middle dielectric layer. The first middle dielectric layer and the second middle dielectric layer are made of dielectric materials. The second metal layer and the first metal layer are made of the same metal material.

公开(公告)号：US11038044B2

公开(公告)日：2021-06-15

申请号：US16585278

申请日：2019-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  I-Sheng Chen

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/311 ,  H01L21/02 ,  H01L29/165 ,  H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L21/308 ,  H01L21/265 ,  H01L29/10

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers.

公开(公告)号：US20210134945A1

公开(公告)日：2021-05-06

申请号：US17120852

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li CHIANG ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  I-Sheng Chen

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088

Abstract: The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages

公开(公告)号：US10727344B2

公开(公告)日：2020-07-28

申请号：US16049273

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  Chih Chieh Yeh ,  Cheng-Hsien Wu ,  Hung-Li Chiang ,  Jung-Piao Chiu ,  Tzu-Chiang Chen ,  Tsung-Lin Lee ,  Yu-Lin Yang ,  I-Sheng Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/165

Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.

公开(公告)号：US20200052131A1

公开(公告)日：2020-02-13

申请号：US16598750

申请日：2019-10-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Sheng Chen ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Carlos H. Diaz

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.

公开(公告)号：US10522694B2

公开(公告)日：2019-12-31

申请号：US15719121

申请日：2017-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng Chen ,  Szu-Wei Huang ,  Hung-Li Chiang ,  Cheng-Hsien Wu ,  Chih Chieh Yeh

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/775 ,  H01L29/04 ,  H01L21/8238 ,  H01L27/04

Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a core region, and one or more shell regions. The core region has an approximately square-shape cross section and a first shell of the one or more shells forms a first shell region of an approximately rhombus-shape cross section around the core region and is connected to an adjacent first shell region corresponding to a neighboring semiconductor wire.

公开(公告)号：US10522345B2

公开(公告)日：2019-12-31

申请号：US16045618

申请日：2018-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Wu ,  I-Sheng Chen

IPC: H01L31/072 ,  H01L31/109 ,  H01L21/02 ,  H01L29/267 ,  H01L29/66 ,  H01L29/78 ,  H01L29/20 ,  H01L29/165 ,  H01L29/06 ,  H01L29/04

Abstract: A method includes receiving a semiconductor substrate including a first semiconductor material; etching a portion of the semiconductor substrate, thereby forming a recess, a bottom portion of the recess having a first sidewall and a second sidewall intersecting with each other, one of the first and second sidewalls exposing a (111) crystallographic plane of the semiconductor substrate; and epitaxially growing a second semiconductor material in the recess, the second semiconductor material having lattice mismatch to the first semiconductor material, dislocations in the second semiconductor material due to the lattice mismatch propagating from the first sidewall to the second sidewall in a direction parallel to a top surface of the semiconductor substrate.