公开(公告)号：US11916122B2

公开(公告)日：2024-02-27

申请号：US17370833

申请日：2021-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Kuan-Ting Pan ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Lo-Heng Chang ,  Chien-Ning Yao ,  Kuo-Cheng Chiang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/401 ,  H01L29/6653 ,  H01L29/78696

Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.

公开(公告)号：US11605737B2

公开(公告)日：2023-03-14

申请号：US17723283

申请日：2022-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Chang Lin ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Lo-Heng Chang ,  Chien-Ning Yao

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

Abstract: A device includes a substrate, a semiconductor layer, a gate structure, source/drain regions, a bottom isolation layer, and a bottom spacer. The semiconductor layer is above the substrate. The gate structure is above the substrate and surrounds the semiconductor layer. The source/drain regions are on opposite sides of the semiconductor layer. The bottom isolation layer is between the substrate and the semiconductor layer. The bottom spacer is on a sidewall of the bottom isolation layer. The bottom isolation layer has a seam therein, and the seam exposes a sidewall of the bottom spacer.

公开(公告)号：US20220359659A1

公开(公告)日：2022-11-10

申请号：US17872439

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Lo-Heng Chang

IPC: H01L29/08 ,  H01L29/66

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises alternately forming first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers include different materials and are stacked up along a direction substantially perpendicular to a top surface of the substrate; forming a dummy gate structure over the first and second semiconductor layers; forming a source/drain (S/D) trench along a sidewall of the dummy gate structure; forming inner spacers between edge portions of the first semiconductor layers, wherein the inner spacers are bended towards the second semiconductor layers; and epitaxially growing a S/D feature in the S/D trench, wherein the S/D feature contacts the first semiconductor layers and includes facets forming a recession away from the inner spacers.

公开(公告)号：US20220320348A1

公开(公告)日：2022-10-06

申请号：US17843332

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lo-Heng Chang ,  Jung-Hung Chang ,  Zhi-Chang Lin ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/02

Abstract: A method of forming a semiconductor device includes forming a fin of alternating layers of semiconductor nanostructures and sacrificial layers, laterally etching sidewall portions of the sacrificial layers, and depositing additional semiconductor material over the sidewalls of the semiconductor nanostructures and sacrificial layers. Following deposition of a dielectric material over the additional semiconductor material and additional etching, the remaining portions of the semiconductor structures and additional semiconductor material collectively form a hammer shape at each opposing side of the fin. Epitaxial source/drain regions formed on the opposing sides of the fin will contact the heads of the hammer shapes.

公开(公告)号：US11430892B2

公开(公告)日：2022-08-30

申请号：US16704110

申请日：2019-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Chih-Hao Wang ,  Pei-Hsun Wang ,  Lo-Heng Chang ,  Jung-Hung Chang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members.

公开(公告)号：US11309424B2

公开(公告)日：2022-04-19

申请号：US16847204

申请日：2020-04-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Chang Lin ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Lo-Heng Chang ,  Chien-Ning Yao

IPC: H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06

Abstract: A semiconductor device includes a substrate, a semiconductor layer, a gate structure, source/drain regions, a bottom isolation layer, and a bottom spacer. The semiconductor layer is above the substrate. The gate structure is above the substrate and surrounds the semiconductor layer. The source/drain regions are on opposite sides of the semiconductor layer. The bottom isolation layer is between the substrate and the semiconductor layer. The bottom spacer is on a sidewall of the bottom isolation layer.

公开(公告)号：US11205711B2

公开(公告)日：2021-12-21

申请号：US16583388

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wang ,  Kuo-Cheng Chiang ,  Lo-Heng Chang ,  Jung-Hung Chang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/306 ,  H01L29/08 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L27/11 ,  H01L29/10

Abstract: A semiconductor device according to the present disclosure includes first gate-all-around (GAA) devices in a first device area and second GAA devices in a second device area. Each of the first GAA devices includes a first vertical stack of channel members, a first gate structure over and around the first vertical stack of channel members, and a plurality of inner spacer features. Each of the second GAA devices includes a second vertical stack of channel members and a second gate structure over and around the second vertical stack of channel members. Two adjacent channel members of the first vertical stack of channel members are separated by a portion of the first gate structure and at least one of the plurality of inner spacer features. Two adjacent channel members of the second vertical stack of channel members are separated only by a portion of the second gate structure.

公开(公告)号：US20210098605A1

公开(公告)日：2021-04-01

申请号：US16583388

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wang ,  Kuo-Cheng Chiang ,  Lo-Heng Chang ,  Jung-Hung Chang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/423 ,  H01L27/11 ,  H01L29/10 ,  H01L29/08 ,  H01L21/306 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device according to the present disclosure includes first gate-all-around (GAA) devices in a first device area and a second GAA devices in a second device area. Each of the first GAA devices includes a first vertical stack of channel members, a first gate structure over and around the first vertical stack of channel members, and a plurality of inner spacer features. Each of the second GAA devices includes a second vertical stack of channel members and a second gate structure over and around the second vertical stack of channel members. Two adjacent channel members of the first vertical stack of channel members are separated by a portion of the first gate structure and at least one of the plurality of inner spacer features. Two adjacent channel members of the second vertical stack of channel members are separated only by a portion of the second gate structure.