公开(公告)号：US20240339526A1

公开(公告)日：2024-10-10

申请号：US18750379

申请日：2024-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Huan-Chieh Su ,  Jia-Chuan You ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Yi-Ruei Jhan ,  Li-Yang Chuang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/6681 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0669

Abstract: A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.

公开(公告)号：US12107153B2

公开(公告)日：2024-10-01

申请号：US18298073

申请日：2023-04-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Kuan-Ting Pan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H10B10/00

CPC classification number: H01L29/6681 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H10B10/12

Abstract: A first semiconductor fin is over the first region of the substrate and extends along a first direction. A second semiconductor fin is over the second region of the substrate and extends along the first direction. A dielectric structure is over the first region of the substrate and is in contact with a longitudinal end of the first semiconductor fin, wherein the dielectric structure is wider than the first semiconductor fin along a second direction perpendicular to the first direction. A first dielectric fin is over the second region of the substrate and is in contact with a longitudinal end of the second semiconductor fin, wherein the first dielectric fin and the second semiconductor fin have substantially a same width along the second direction.

公开(公告)号：US11961763B2

公开(公告)日：2024-04-16

申请号：US17224334

申请日：2021-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Chuan You ,  Kuan-Ting Pan ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/76897 ,  H01L21/02603 ,  H01L21/76805 ,  H01L21/76871 ,  H01L21/76895 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/53257 ,  H01L23/535 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Devices and methods that a first gate structure wrapping around a channel layer disposed over the substrate, a second gate structure wrapping around another channel layer disposed over the substrate and a dielectric fin structure formed over a shallow trench isolation (STI) feature and between the first and second gate structures. At least one metallization layer is formed on the first gate structure, the dielectric fin structure, and the second gate structure and contiguously extends from the first gate structure to the second gate structure.

公开(公告)号：US11948973B2

公开(公告)日：2024-04-02

申请号：US17402985

申请日：2021-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Huan-Chieh Su ,  Shi Ning Ju ,  Kuan-Ting Pan ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/0886 ,  H01L29/1033 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/66545

Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.

公开(公告)号：US11637102B2

公开(公告)日：2023-04-25

申请号：US17199777

申请日：2021-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Guan-Lin Chen ,  Kuan-Ting Pan ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/762 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  B82Y10/00

Abstract: Gate cutting techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap may be disposed on the gate isolation fin to provide additional isolation.

公开(公告)号：US20220344333A1

公开(公告)日：2022-10-27

申请号：US17476418

申请日：2021-09-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Ruei Jhan ,  Kuan-Ting Pan ,  Shi-Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, an isolation feature embedded in the substrate and laterally between the first and second semiconductor channels, a first liner layer laterally surrounding the isolation feature between the isolation feature and the first semiconductor channel, and a second liner layer laterally surrounding the first liner layer between the first liner layer and the first semiconductor channel.

公开(公告)号：US20220238384A1

公开(公告)日：2022-07-28

申请号：US17717429

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ting Lan ,  Kuan-Ting Pan ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L21/306 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/321 ,  H01L21/762

Abstract: According to one example, a semiconductor device includes a first region comprising a plurality of nanosheets vertically stacked above a substrate, a second region comprising a fin protruding from the substrate, a first gate structure wrapping around each of the nanosheets, and a second gate structure disposed over the top surface and sidewalls of the fin. A top surface of a topmost nanosheet of the plurality of nanosheets is vertically offset from a top surface of the fin.

公开(公告)号：US11355398B2

公开(公告)日：2022-06-07

申请号：US17027282

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuan-Ting Pan ,  Kuo-Cheng Chiang ,  Shang-Wen Chang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/768

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.

公开(公告)号：US11302580B2

公开(公告)日：2022-04-12

申请号：US16888380

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ting Lan ,  Kuan-Ting Pan ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/306 ,  H01L29/06 ,  H01L21/321 ,  H01L27/088 ,  H01L29/78

Abstract: According to one example, a method includes performing a Chemical Mechanical Polishing (CMP) process on a semiconductor workpiece that includes a nanosheet region, the nanosheet region having alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes stopping the CMP process when the first type of semiconductor material is covered by the second type of semiconductor material, patterning the nanosheet region to form nanosheet stacks, forming an isolation structure around the nanosheet stacks, removing a top layer of the second type of semiconductor material from the nanosheet stacks, recessing the isolation structure, and forming a gate structure over the nanosheet stacks.

公开(公告)号：US10825918B2

公开(公告)日：2020-11-03

申请号：US16260483

申请日：2019-01-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Zhi-Chang Lin ,  Kuan-Ting Pan ,  Chih-Hao Wang ,  Shi-Ning Ju

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/033 ,  H01L27/088

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure extending above an isolation structure. The semiconductor device structure includes a dummy fin structure formed over the isolation structure, and the dummy fin structure is between the first fin structure and the second fin structure. The semiconductor device structure includes a capping layer formed over the dummy fin structure, and the top surface of the capping layer is higher than the top surface of the first fin structure and the top surface of the second fin structure. The semiconductor device structure includes a first gate structure formed over first fin structure, and a second gate structure formed over the second fin structure. The first gate structure and the second gate structure are separated by the dummy fin structure and the capping layer.