公开(公告)号：US11380772B2

公开(公告)日：2022-07-05

申请号：US17012832

申请日：2020-09-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei Fang

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8238

Abstract: A semiconductor device and a method of forming the same are provided. In one embodiment, the semiconductor device includes a semiconductor substrate, a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions, and a plurality of gate structures. The plurality of gate structures includes an interfacial layer (IL) disposed over the plurality of channel regions, a first high-k (HK) dielectric layer disposed over the first p-type channel region and the first n-type channel region, a second high-k dielectric layer disposed over the first n-type channel region, the second n-type channel region, the first p-type channel region, and the second p-type channel region; and a third high-k dielectric layer disposed over the plurality of channel regions. The first, second and third high-k dielectric layers are different from one another.

公开(公告)号：US11373910B2

公开(公告)日：2022-06-28

申请号：US16897229

申请日：2020-06-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yasutoshi Okuno ,  Cheng-Yi Peng ,  Ziwei Fang ,  I-Ming Chang ,  Akira Mineji ,  Yu-Ming Lin ,  Meng-Hsuan Hsiao

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/203 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L27/12 ,  H01L21/84 ,  H01L29/161

Abstract: A method of forming a semiconductor device including a fin field effect transistor (FinFET), the method includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer made of Si1-y-a-bGeaSnbM2y, wherein 0

公开(公告)号：US11251087B2

公开(公告)日：2022-02-15

申请号：US16897234

申请日：2020-06-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yasutoshi Okuno ,  Cheng-Yi Peng ,  Ziwei Fang ,  I-Ming Chang ,  Akira Mineji ,  Yu-Ming Lin ,  Meng-Hsuan Hsiao

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/203 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L27/12 ,  H01L21/84 ,  H01L29/161

Abstract: A method of forming a semiconductor device including a fin field effect transistor (FinFET) includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer including Si1−x−yM1xM2y, where M1 includes Sn, M2 is one or more of P and As, and 0.01≤x≤0.1, and 0.01≤y≤0.1.

公开(公告)号：US11251078B2

公开(公告)日：2022-02-15

申请号：US16745769

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei Fang

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/285

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first conductive feature over a semiconductor substrate. The method includes forming an oxygen-absorbing layer on a surface of the first conductive feature. The oxygen-absorbing layer absorbs oxygen from the first conductive feature and becomes an oxygen-containing layer. The method includes removing the oxygen-containing layer to expose the surface originally covered by the oxygen-containing layer. The method includes forming a metal-containing layer on the surface. The method includes forming a second conductive feature on the metal-containing layer.

公开(公告)号：US11211244B2

公开(公告)日：2021-12-28

申请号：US16745532

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Christine Y. Ouyang ,  Ziwei Fang

IPC: H01L21/00 ,  H01L21/02 ,  C23C16/02 ,  C23C16/455 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/285

Abstract: The present disclosure relates to a method of fabricating a semiconductor structure, the method includes forming an opening and depositing a metal layer in the opening. The depositing includes performing one or more deposition cycles, wherein each deposition cycle includes flowing a first precursor into a deposition chamber and performing an ultraviolet (UV) radiation process on the first precursor. The method further includes performing a first purging process in the deposition chamber to remove at least a portion of the first precursor, flowing a second precursor into the deposition chamber, and purging the deposition chamber to remove at least a portion of the second precursor.

公开(公告)号：US11201060B2

公开(公告)日：2021-12-14

申请号：US16386519

申请日：2019-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Christine Y Ouyang ,  Ziwei Fang

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/02 ,  H01L21/31 ,  H01L21/32 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming a spacer element over a sidewall of the dummy gate stack. The method also includes removing the dummy gate stack to form a recess exposing a semiconductor strip and forming an inhibition layer over an interior surface of the spacer element. The method further includes forming a gate dielectric layer in the recess to selectively cover the semiconductor strip. The inhibition layer substantially prevents the gate dielectric layer from being formed on the inhibition layer. In addition, the method includes forming a metal gate electrode over the gate dielectric layer.

公开(公告)号：US11177259B2

公开(公告)日：2021-11-16

申请号：US16585267

申请日：2019-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  I-Ming Chang ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

Abstract: The present disclosure describes a semiconductor device that includes a semiconductor device that includes a first transistor having a first gate structure. The first gate structure includes a first gate dielectric layer doped with a first dopant at a first dopant concentration and a first work function layer on the first gate dielectric layer. The first gate structure also includes a first gate electrode on the first work function layer. The semiconductor device also includes a second transistor having a second gate structure, where the second gate structure includes a second gate dielectric layer doped with a second dopant at a second dopant concentration lower than the first dopant concentration. The second gate structure also includes a second work function layer on the second gate dielectric layer and a second gate electrode on the second work function layer.

公开(公告)号：US20210328064A1

公开(公告)日：2021-10-21

申请号：US17328145

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming LIN ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Chi On Chui ,  Huang-Lin Chao

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

公开(公告)号：US20210296503A1

公开(公告)日：2021-09-23

申请号：US17339615

申请日：2021-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Chi On Chui ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66

Abstract: A semiconductor structure includes gate spacers disposed over a semiconductor layer, a hafnium-containing dielectric layer, where a first portion of the hafnium-containing dielectric layer having a first thickness is disposed over the semiconductor layer and a second portion of the hafnium-containing dielectric layer having a second thickness is disposed along sidewalls of the gate spacers, and where the first thickness is greater than the second thickness, and a metal gate electrode disposed over the hafnium-containing dielectric layer and between the gate spacers.

公开(公告)号：US11088034B2

公开(公告)日：2021-08-10

申请号：US16739676

申请日：2020-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei Fang

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L27/092 ,  H01L29/49 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/28

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second nanostructured channel regions in first and second nanostructured layers, respectively, and first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The first GAA structure includes an Al-based gate stack with a first gate dielectric layer, an Al-based n-type work function metal layer, a first metal capping layer, and a first gate metal fill layer. The second GAA structure includes an Al-free gate stack with a second gate dielectric layer, an Al-free p-type work function metal layer, a metal growth inhibition layer, a second metal capping layer, and a second gate metal fill layer.