公开(公告)号：US20240021564A1

公开(公告)日：2024-01-18

申请号：US18366947

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/14

CPC classification number: H01L24/29 ,  H01L24/14 ,  H01L24/05 ,  H01L24/81 ,  H01L23/3128 ,  H01L23/14 ,  H01L2224/8234 ,  H01L2924/35 ,  H01L2224/0401 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/2101 ,  H01L2224/2902 ,  H01L2224/14104 ,  H01L2224/8134

Abstract: A semiconductor device includes a redistribution structure, an integrated circuit package attached to a first side of the redistribution structure and a core substrate coupled to a second side of the redistribution structure with a first conductive connector and a second conductive connector. The second side is opposite the first side. The semiconductor device further includes a top layer of the core substrate including a dielectric material and a chip disposed between the redistribution structure and the core substrate. The chip is interposed between sidewalls of the dielectric material.

公开(公告)号：US20240021506A1

公开(公告)日：2024-01-18

申请号：US18447008

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/49833 ,  H01L23/562 ,  H01L23/49866 ,  H01L23/49816 ,  H01L23/49827

Abstract: A semiconductor device and method of manufacture is provided including a redistribution structure; a plurality of core substrates attached to the redistribution structure using conductive connectors, each core substrate of the plurality of core substrates comprising a plurality of conductive posts; and one or more molding layers encapsulating the plurality of core substrates, where the one or more molding layers extends along sidewalls of the plurality of core substrates, and where the one or more molding layers extends along a portion of a sidewall of each of the conductive posts.

公开(公告)号：US20230386986A1

公开(公告)日：2023-11-30

申请号：US18446006

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/16

CPC classification number: H01L23/49822 ,  H01L28/40 ,  H01L23/49827 ,  H01L23/49816 ,  H01L21/4857 ,  H01L21/486 ,  H01L25/16

Abstract: A package includes a first layer of molding material, a first metallization layer on the first layer of molding material, a second layer of molding material on the first metallization layer and the first layer of molding material, a second metallization layer on the second layer of molding material, through vias within the second layer of molding material, the through vias extending from the first metallization layer to the second metallization layer, integrated passive devices within the second layer of molding material, a redistribution structure electrically on the second metallization layer and the second layer of molding material, the redistribution structure connected to the through vias and the integrated passive devices, and at least one semiconductor device on the redistribution structure, the at least one semiconductor device connected to the redistribution structure.

公开(公告)号：US20230060716A1

公开(公告)日：2023-03-02

申请号：US17412625

申请日：2021-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L21/768 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: In an embodiment, a structure includes a core substrate, a redistribution structure coupled to a first side of the core substrate, the redistribution structure including a plurality of redistribution layers, each of the plurality of redistribution layers comprising a dielectric layer and a metallization layer, and a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component including a substrate, an interconnect structure on the substrate, and bond pads on the interconnect structure, the bond pads of the first local interconnect component physically contacting a metallization layer of a second redistribution layer, the second redistribution layer being adjacent the first redistribution layer, the metallization layer of the second redistribution layer comprising first conductive vias, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component.

公开(公告)号：US20220367333A1

公开(公告)日：2022-11-17

申请号：US17874062

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L21/48

Abstract: An integrated circuit package that includes symmetrical redistribution structures on either side of a core substrate is provided. In an embodiment, a device comprises a core substrate, a first redistribution structure comprising one or more layers, a second redistribution comprising one or more layers, a first integrated circuit die, and a set of external conductive features. The core substrate is disposed between the first redistribution structure and the second redistribution structure, the first integrated circuit die is disposed on the first distribution structure on the opposite side from the core substrate; and the set of external conductive features are disposed on a side of the second redistribution structure opposite the core substrate. The first redistribution structure and second redistribution structure have symmetrical redistribution layers to each other with respect to the core substrate.

公开(公告)号：US20220359460A1

公开(公告)日：2022-11-10

申请号：US17869034

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Shang-Yun Hou

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor device includes a first Chip-On-Wafer (CoW) device having a first interposer and a first die attached to a first side of the first interposer; a second CoW device having a second interposer and a second die attached to a first side of the second interposer, the second interposer being laterally spaced apart from the first interposer; and a redistribution structure extending along a second side of the first interposer opposing the first side of the first interposer and extending along a second side of the second interposer opposing the first side of the second interposer, the redistribution structure extending continuously from the first CoW device to the second CoW device.

公开(公告)号：US20220359327A1

公开(公告)日：2022-11-10

申请号：US17870222

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chien-Hsun Lee ,  Jiun Yi Wu

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56

Abstract: An integrated fan out package is utilized in which the dielectric materials of different redistribution layers are utilized to integrate the integrated fan out package process flows with other package applications. In some embodiments an Ajinomoto or prepreg material is utilized as the dielectric in at least some of the overlying redistribution layers.

公开(公告)号：US20220278066A1

公开(公告)日：2022-09-01

申请号：US17186775

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/14

Abstract: A semiconductor device includes a redistribution structure, an integrated circuit package attached to a first side of the redistribution structure and a core substrate coupled to a second side of the redistribution structure with a first conductive connector and a second conductive connector. The second side is opposite the first side. The semiconductor device further includes a top layer of the core substrate including a dielectric material and a chip disposed between the redistribution structure and the core substrate. The chip is interposed between sidewalls of the dielectric material.

公开(公告)号：US11355463B2

公开(公告)日：2022-06-07

申请号：US17020130

申请日：2020-09-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/00

Abstract: In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.

公开(公告)号：US20220173003A1

公开(公告)日：2022-06-02

申请号：US17650932

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Chung-Shi Liu

IPC: H01L23/31 ,  H01L21/56

Abstract: A method includes placing a package component over a carrier. The package component includes a device die. A core frame is placed over the carrier. The core frame forms a ring encircling the package component. The method further includes encapsulating the core frame and the package component in an encapsulant, forming redistribution lines over the core frame and the package component, and forming electrical connectors over and electrically coupling to the package component through the redistribution lines.