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公开(公告)号:US09577049B1
公开(公告)日:2017-02-21
申请号:US14989259
申请日:2016-01-06
发明人: Shih-Yen Lin , Chong-Rong Wu , Chi-Wen Liu
IPC分类号: H01L29/24 , H01L29/45 , H01L29/417 , H01L29/78 , H01L29/66 , H01L21/443
CPC分类号: H01L21/443 , H01L29/41733 , H01L29/45 , H01L29/4908 , H01L29/66969 , H01L29/78 , H01L29/78618 , H01L29/78681
摘要: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a semiconductor layer over the substrate. The semiconductor layer includes a transition metal chalcogenide. The semiconductor device structure includes a source electrode and a drain electrode over and connected to the semiconductor layer and spaced apart from each other by a gap. The source electrode and the drain electrode are made of graphene.
摘要翻译: 提供半导体器件结构。 半导体器件结构包括衬底。 半导体器件结构包括在衬底上的半导体层。 半导体层包括过渡金属硫族化物。 半导体器件结构包括在半导体层之上并连接到半导体层并且通过间隙彼此间隔开的源电极和漏电极。 源电极和漏电极由石墨烯制成。
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公开(公告)号:US09525072B2
公开(公告)日:2016-12-20
申请号:US14455992
申请日:2014-08-11
发明人: Meng-Yu Lin , Shih-Yen Lin , Si-Chen Lee
IPC分类号: H01L29/786 , H01L29/16 , H01L29/423 , H01L29/49 , H01L29/66
CPC分类号: H01L29/1606 , H01L29/42356 , H01L29/42384 , H01L29/42392 , H01L29/4908 , H01L29/66015 , H01L29/78603 , H01L29/78648 , H01L29/78684 , H01L29/78696 , H01L2924/13088
摘要: A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided.
摘要翻译: 提供了半导体器件和形成方法。 半导体器件包括衬底,衬底上的第一有源区,衬底上的第二有源区,第一有源区和第二有源区之间的石墨烯通道,以及第一平面栅极。 在一些实施例中,石墨烯通道,第一面内栅极,第一有源区域和第二有源区域包括石墨烯。 还提供了从单层石墨烯形成第一面内栅极,第一有源区域,第二有源区域和石墨烯通道的方法。
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公开(公告)号:US10269902B2
公开(公告)日:2019-04-23
申请号:US15852391
申请日:2017-12-22
发明人: Meng-Yu Lin , Shih-Yen Lin , Si-Chen Lee
IPC分类号: H01L29/16 , H01L29/66 , H01L29/10 , H01L29/786 , H01L29/423 , H01L29/49
摘要: A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided.
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34.
公开(公告)号:US10269564B2
公开(公告)日:2019-04-23
申请号:US15726038
申请日:2017-10-05
发明人: Shih-Yen Lin , Kuan-Chao Chen , Si-Chen Lee , Samuel C. Pan
IPC分类号: H01L29/786 , H01L29/24 , H01L29/66 , H01L29/15 , H01L21/336 , H01L29/861 , H01L21/02 , B01J27/045 , H01L29/778 , C01G39/06 , H01L29/267 , H01L29/417 , H01L29/10 , H01L21/3065 , C01B32/186
摘要: A method of fabricating a semiconductor device includes plasma etching a portion of a plurality of metal dichalcogenide films comprising a compound of a metal and a chalcogen disposed on a substrate by applying a plasma to the plurality of metal dichalcogenide films. After plasma etching, a chalcogen is applied to remaining portions of the plurality of metal dichalcogenide films to repair damage to the remaining portions of the plurality of metal dichalcogenide films from the plasma etching. The chalcogen is S, Se, or Te.
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公开(公告)号:US10164122B2
公开(公告)日:2018-12-25
申请号:US15884729
申请日:2018-01-31
发明人: Shih-Yen Lin , Chi-Wen Liu , Chong-Rong Wu , Xiang-Rui Chang
IPC分类号: H01L21/02 , H01L29/786 , H01L29/66 , H01L29/24 , H01L29/778 , H01L29/267 , H01L29/417 , H01L29/16
摘要: A method includes depositing a first transition metal film having a first transition metal on a substrate and performing a first sulfurization process to the first transition metal film, thereby forming a first transition metal sulfide film. The method further includes depositing a second transition metal film having a second transition metal on the first transition metal sulfide film and performing a second sulfurization process to the second transition metal film, thereby forming a second transition metal sulfide film. The first and the second transition metals are different. The method further includes forming a gate stack, and source and drain features over the second transition metal sulfide film. The gate stack is interposed between the source and drain features. The gate stack, source and drain features, the first transition metal sulfide film and the second transition metal sulfide film are configured to function as a hetero-structure transistor.
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公开(公告)号:US11152209B2
公开(公告)日:2021-10-19
申请号:US16712570
申请日:2019-12-12
发明人: Shih-Yen Lin , Hsuan-An Chen , Si-Chen Lee
IPC分类号: H01L29/16 , H01L21/02 , H01L29/24 , H01L29/267
摘要: The current disclosure describes semiconductor devices, e.g., transistors, include a substrate, a semiconductor region including, at the surface, MoS2 and/or other monolayer material over the substrate, and a terminal structure at least partially over the semiconductor region, which includes a different monolayer material grown directly over the semiconductor region.
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公开(公告)号:US11121214B2
公开(公告)日:2021-09-14
申请号:US16548744
申请日:2019-08-22
发明人: Shih-Yen Lin , Kuan-Chao Chen , Hsuan-An Chen , Lun-Ming Lee
IPC分类号: H01L29/06 , H01L29/24 , H01L21/283 , H01L29/768 , H01L29/66 , H01L29/45
摘要: A semiconductor device includes a substrate, semiconductor 2-D material layer, a conductive 2-D material layer, a gate dielectric layer, and a gate electrode. The semiconductor 2-D material layer is over the substrate. The conductive 2-D material layer extends along a source/drain region of the semiconductor 2-D material layer, in which the conductive 2-D material layer comprises a group-IV element. The gate dielectric layer extends along a channel region of the semiconductor 2-D material layer. The gate electrode is over the gate dielectric layer.
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38.
公开(公告)号:US10985019B2
公开(公告)日:2021-04-20
申请号:US16859822
申请日:2020-04-27
发明人: Shih-Yen Lin , Kuan-Chao Chen , Si-Chen Lee , Samuel C. Pan
IPC分类号: H01L27/115 , H01L27/1159 , H01L29/792 , H01L29/78 , H01L29/04 , H01L21/02 , B01J27/045 , H01L29/778 , C01G39/06 , H01L29/267 , H01L29/417 , H01L29/66 , H01L29/786 , H01L29/10 , H01L29/24 , H01L21/3065 , C01B32/186
摘要: A method of fabricating a semiconductor device includes plasma etching a portion of a plurality of metal dichalcogenide films comprising a compound of a metal and a chalcogen disposed on a substrate by applying a plasma to the plurality of metal dichalcogenide films. After plasma etching, a chalcogen is applied to remaining portions of the plurality of metal dichalcogenide films to repair damage to the remaining portions of the plurality of metal dichalcogenide films from the plasma etching. The chalcogen is S, Se, or Te.
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公开(公告)号:US10147603B2
公开(公告)日:2018-12-04
申请号:US15197004
申请日:2016-06-29
发明人: Shih-Yen Lin , Chi-Wen Liu , Si-Chen Lee , Chong-Rong Wu , Kuan-Chao Chen
IPC分类号: H01L21/336 , H01L21/02 , H01L21/324 , H01L29/66
摘要: In a method of fabricating a field effect transistor, a Mo layer is formed on the substrate. The Mo layer is sulfurized to convert it into a MoS2 layer. Source and drain electrodes are formed on the MoS2 layer. The MoS2 layer is treated with low-power oxygen plasma. A gate dielectric layer is formed on the MoS2 layer. A gate electrode is formed on the gate dielectric layer. An input electric power in the low-power oxygen plasma treatment is in a range from 15 W to 50 W.
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公开(公告)号:US20170098693A1
公开(公告)日:2017-04-06
申请号:US15381047
申请日:2016-12-15
发明人: Meng-Yu Lin , Shih-Yen Lin , Si-Chen Lee
IPC分类号: H01L29/16 , H01L29/786 , H01L29/423
CPC分类号: H01L29/1606 , H01L29/42356 , H01L29/42384 , H01L29/42392 , H01L29/4908 , H01L29/66015 , H01L29/78603 , H01L29/78648 , H01L29/78684 , H01L29/78696 , H01L2924/13088
摘要: A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided.
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